Hi Matthias,
Can you please let me know how following three values are calculated in
your patch. I am trying to understand how do I change it for my board.
port->board.base_baud = 4000000;
port->board.port_offset = 0x200;
port->board.base_offset = 0x1000;
On Fri, Mar 24, 2017 at 10:59 PM, Gailu Singh <gail...@gmail.com> wrote:
> Hi Matthias,
>
> The patches I send to the mailing list do not support the Intel UARTs
> right now, because they only match for OXSemi IDs. One has to add a
> similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs.
>
> I have changed the ns8250_pci_mmio_iter and enabled two debug print in
> ns8250-pci-mmio.c and I see following prints.
>
> Found Intel PCI UART
>
> bar=c2539004 (MEM, sz=4)
> bar=c2539004 (MEM, sz=4)
>
> in my grub.cfg I have
>
> serial --port=pci:0:0 --speed=115200
> terminal_input --append serial_pci:0:0
> terminal_output --append serial_pci:0:0
>
> But I do not see any output on my serial console. I changed board.base_baud
> from 4000000 to 115200. Any other debug print that I could enable to
> proceed further on this?
>
> My changed code
> -----------------------------------
> static int
> ns8250_pci_mmio_iter(grub_pci_device_t dev, grub_pci_id_t pciid, void
> *data)
> {
> unsigned vendor, device;
> struct drv_data *d = (struct drv_data *)data;
>
> if (d->num_ports >= GRUB_SERIAL_PCI_PORT_NUM)
> return 0;
>
> vendor = pciid & 0xffff;
> device = pciid >> 16;
>
> if (vendor == 0x8086 && device == 0x5ac0)
> {
> struct grub_serial_port *port = &ports[d->num_ports];
> struct grub_serial_board *b = &ports[d->num_ports].board;
>
> if (1)
> grub_printf("Found Intel PCI UART\n");
>
> read_bars(dev, b);
>
> port->board.num_ports = 1;
> port->board.base_baud = 115200;
> port->board.port_offset = 0x200;
> port->board.base_offset = 0x1000;
>
> port->pcidev.bus = dev.bus;
> port->pcidev.device = dev.device;
> port->pcidev.function = dev.function;
> port->port_num = 0;
> port->card = d->cards;
> port->mmio_base = port->board.bars[0].base + port->board.base_offset
> +
> port->port_num * port->board.port_offset;
> d->num_ports += 1;
>
> if (d->num_ports >= GRUB_SERIAL_PCI_PORT_NUM)
> return 0;
>
> enable_mmio (dev);
> d->cards += 1;
> }
>
> return 0;
> }
> -----------------
>
>
> On Fri, Mar 3, 2017 at 7:11 PM, Matthias Lange <
> matthias.la...@kernkonzept.com> wrote:
>
>> Hi,
>>
>> On 03/03/2017 01:03 PM, Gailu Singh wrote:
>> > Sorry it took some time to boot board with Linux. Not sure how to
>> > determine correct Device ID, Vendor ID seems to be all 8086 on the oard
>> > My lspci -nn command output is
>> >
>> > root@localhost:~# lspci -nn
>>
>> [...]
>>
>> > 00:18.0 Signal processing controller [1180]: Intel Corporation Device
>> > [8086:5abc] (rev 0b)
>> > 00:18.1 Signal processing controller [1180]: Intel Corporation Device
>> > [8086:5abe] (rev 0b)
>> > 00:18.2 Signal processing controller [1180]: Intel Corporation Device
>> > [8086:5ac0] (rev 0b)
>> > 00:18.3 Signal processing controller [1180]: Intel Corporation Device
>> > [8086:5aee] (rev 0b)
>>
>> These four devices are the HSUARTs (high speed UART). According to the
>> documentation they are 16550A compatible UARTs.
>>
>> [...]
>>
>> The patches I send to the mailing list do not support the Intel UARTs
>> right now, because they only match for OXSemi IDs. One has to add a
>> similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs.
>>
>> First I need to have a look into the Linux driver to get more insights.
>> If I am lucky we also might have a board with an Intel Quark SoC flying
>> around in the office.
>>
>> Best,
>> Matthias.
>>
>> >
>> > In coreboot it initializes as
>> >
>> > uintptr_t uart_platform_base(int idx)
>> > {
>> > u8 *pcie;
>> > u32 tmp;
>> > idx = idx & 3;
>> > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0);
>> > tmp = read32 (pcie + PCI_BASE_ADDRESS_0);
>> > if (tmp == 0xFFFFFFFF) {
>> > /* the device might be hidden */
>> > return LPSS_UART_BASE_ADDRESS;
>> > } else {
>> > return (uintptr_t) (tmp & 0xFFFFFFF0);
>> > }
>> > }
>> >
>> > #define PCIE_MMIO(Bus, Device, Function, Register ) \
>> > ( (UINTN)CONFIG_MMCONF_BASE_ADDRESS + \
>> > (UINTN)(Bus << 20) + \
>> > (UINTN)(Device << 15) + \
>> > (UINTN)(Function << 12) + \
>> > (UINTN)(Register) \
>> > )
>> >
>> >
>> > #define PCH_DEV_SLOT_UART0x18
>> >
>> > There are 4 uarts (idx 0 to 3)
>> >
>> > Is above information sufficient to find the required information?
>> >
>> > On Wed, Mar 1, 2017 at 4:34 PM, Gailu Singh <gail...@gmail.com
>> > <mailto:gail...@gmail.com>> wrote:
>> >
>> > Build problem was due to not running ./configure. I only did make
>> > clean and make. Build issue is now resolved after running
>> > configure. Only cosmetic change in your patch.
>> >
>> > =============
>> > static void
>> > read_bars(grub_pci_device_t dev, struct grub_serial_board *board)
>> > {
>> > for (unsigned bar = 0; bar < NUM_BARS; ++bar)
>> >
>> > changed to
>> > =============
>> > static void
>> > read_bars(grub_pci_device_t dev, struct grub_serial_board *board)
>> > {
>> > unsigned bar;
>> >
>> > for (bar = 0; bar < NUM_BARS; ++bar)
>> > ============
>> >
>> > I was getting error for C99 enforcement error during build(‘for’
>> > loop initial declarations are only allowed in C99 mode)
>> >
>> >
>> > I will check PCI vendor ID and Device ID and get back to you.
>> >
>> >
>> >
>> > On Wed, Mar 1, 2017 at 4:27 PM, Matthias Lange
>> > <matthias.la...@kernkonzept.com
>> > <mailto:matthias.la...@kernkonzept.com>> wrote:
>> >
>> > On 03/01/2017 11:32 AM, Gailu Singh wrote:
>> > > I checked coreboot where in the memory it is mapped and it
>> seems to be
>> > > on PCIE. Relevant code from coreboot. So I am hopeful that
>> patch will work.
>> > > ---------
>> > > uintptr_t uart_platform_base(int idx)
>> > > {
>> > > u8 *pcie;
>> > > u32 tmp;
>> > > idx = idx & 3;
>> > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0);
>> > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0);
>> > > if (tmp == 0xFFFFFFFF) {
>> > > /* the device might be hidden */
>> > > return LPSS_UART_BASE_ADDRESS;
>> > > } else {
>> > > return (uintptr_t) (tmp & 0xFFFFFFF0);
>> > > }
>> > > }
>> > > ---------
>> >
>> > This looks promising. Could you extract the PCI vendor and
>> device ID
>> > please? My current implementation currently only supports OXSemi
>> > chips.
>> >
>> > > I applied the patches and run make clean followed by make
>> but build
>> > > failed as follows
>> > > ------------------------
>> > > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst
>> || (rm -f
>> > > moddep.lst; exit 1)
>> > > grub_ns8250_pci_mmio_init in serial is not defined
>> > > make[3]: *** [moddep.lst] Error 1
>> > > ------------------------
>> >
>> > Hmmm, grub_ns8250_pci_mmio_init is defined in
>> include/grub/serial.h.
>> > Could you check that please? I failed to reproduce your problem,
>> > maybe I
>> > did something different?
>> >
>> > (master checked out)
>> > /tmp/grub $ /path/to/grub-src/configure --with-platform=efi
>> > /tmp/grub $ make -j12 # success
>> > (applied my three patches)
>> > /tmp/grub $ make clean
>> > /tmp/grub $ make -j12 # success
>> >
>> > Matthias.
>> >
>> > > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <
>> gail...@gmail.com <mailto:gail...@gmail.com>
>> > > <mailto:gail...@gmail.com <mailto:gail...@gmail.com>>> wrote:
>> > >
>> > > Sorry for typo. I meant 8250 instead of 8050 in last email
>> > >
>> > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh <
>> gail...@gmail.com <mailto:gail...@gmail.com>
>> > > <mailto:gail...@gmail.com <mailto:gail...@gmail.com>>>
>> wrote:
>> > >
>> > > My board is Intel Oxbohill CRB (Apollo lake). On my
>> board UART
>> > > are not connected to PCI.
>> > >
>> > > I am using grub2 payload loaded by coreboot. UART
>> works fine in
>> > > coreboot by using memory mapped 8050 driver
>> > > (https://github.com/coreboot/
>> coreboot/blob/master/src/drivers/uart/uart8250mem.c
>> > <https://github.com/coreboot/coreboot/blob/master/src/drive
>> rs/uart/uart8250mem.c>
>> > >
>> > <https://github.com/coreboot/coreboot/blob/master/src/driver
>> s/uart/uart8250mem.c
>> > <https://github.com/coreboot/coreboot/blob/master/src/drive
>> rs/uart/uart8250mem.c>>),
>> > > however when grub2 is loaded it refuses to recognize
>> UART.
>> > >
>> > >
>> > >
>> > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange
>> > > <matthias.la...@kernkonzept.com
>> > <mailto:matthias.la...@kernkonzept.com>
>> > > <mailto:matthias.la...@kernkonzept.com
>> > <mailto:matthias.la...@kernkonzept.com>>> wrote:
>> > >
>> > > Hi,
>> > >
>> > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote:
>> > > > please test patches from Matthias Lange
>> > > >
>> > > > https://lists.gnu.org/archive/
>> html/grub-devel/2017-02/msg00104.html
>> > <https://lists.gnu.org/archive/html/grub-devel/2017-02/
>> msg00104.html>
>> > > <https://lists.gnu.org/archiv
>> e/html/grub-devel/2017-02/msg00104.html
>> > <https://lists.gnu.org/archive/html/grub-devel/2017-02/
>> msg00104.html>>
>> > > >
>> > > >
>> > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh
>> > <gail...@gmail.com <mailto:gail...@gmail.com>
>> > <mailto:gail...@gmail.com <mailto:gail...@gmail.com>>> wrote:
>> > > >> Hi Experts,
>> > > >>
>> > > >> I am using GRUB2 on intel apollo lake board.
>> > This board does not have IO
>> > > >> mapped uart instead it has 8250 memory mapped
>> UART.
>> > >
>> > > Could you share some details about the board?
>> > >
>> > > >> GRUB2 does not recognize memory mapped uart and
>> > gives error ("serial port
>> > > >> COM0 not found). There is a 8250 memory mapped
>> > driver available in coreboot.
>> > > >> Is it possible to port that driver to Grub2?
>> > >
>> > > My patch set adds support for 8250 MMIO PCI cards.
>> > Is the
>> > > UART on your
>> > > board connected via PCI?
>> > >
>> > > Best,
>> > > Matthias.
>>
>>
>> --
>> Matthias Lange, matthias.la...@kernkonzept.com, +49-351-41 888 614
>>
>> Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129.
>> Geschäftsführer: Dr.-Ing. Michael Hohmuth
>>
>>
>
_______________________________________________
Grub-devel mailing list
Grub-devel@gnu.org
https://lists.gnu.org/mailman/listinfo/grub-devel
