In a message dated 7/14/2005 10:22:13 A.M. Central Daylight Time,  
[EMAIL PROTECTED] writes:

Might  this also depend on whether the storage operand is
doubleword aligned, and  whether the registers are an
even/odd pair?
It definitely depends on the alignment of the storage operand.  This  is one 
of the 853 variables I mentioned (a slight exaggeration or a SWAG, but  there 
are a LOT of variables).  Even/odd pair I don't know about.   Wouldn't 
surprise me.

I once  heard a rumor that there was special millicode to optimize
"STM  R14,R12".
I missed that rumor, but it could be.  IBM invented special opcodes to  
handle certain very frequently executed functions in MVS and many other 
software  
products that run on their mainframes (CP, VS1, e.g.).  They were  documented 
in the MVS Assist Feature book, but still not in the z/Arch. Princ.  Ops.  Too 
operating system-specific I supposed.  E.g., Add FRR is B242  (where was 
remove FRR?), obtain/release local lock, fix page.  The squeaky  wheel ought to 
get 
more grease than the others.

A  programmer I know once discovered that (on a 148?) LM; STM
moved a  doubleword faster than MVC.  He accordingly updated all
his assembly  code.  He was livid when we got a Magnusson M80,
marketed to compete  with the 148, and discovered that MVC
was faster than LM; STM.  A true  Blue partisan, he had to
confront the choice of optimizing his code for  competing hardware
or leaving it suboptimal.  He was not in the least  soothed that
the M80 executed neither instruction slower than the  148.
A very good reason not to care or to be partisan.

> And  in any case "who cares"?


Best reason of all.  Time saved is in the order of nanoseconds; time  spent 
on discussing, thinking about, different keystrokes, etc., far outweighs  the 
benefit UNLESS the code is executed thousands of times per second in  critical 
paths, like disabled interrupt processors, the Dispatcher, adding FRRs,  etc.
 
Bill Fairchild

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