The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
[EMAIL PROTECTED] (Shmuel Metz , Seymour J.) writes: > 8 bits of ECC for 64 bits of data. > > At one point the trade press was talking about low cost block oriented > random access memory (BORAM), which would have been a natural for ES. > Unfortunately, that doesn't seem to have materialized, or at least > BORAM failed to maintain an adequate price lead. from previous post http://www.garlic.com/~lynn/2006r.html#36 REAL memory column in SDSF reference in previous post http://www.research.ibm.com/journal/rd/435/spainhower.pdf ... from reference above: When a chip is b bits (b =|> 2) wide, an access to a 64-bit data word may have a b-bit block or byte error. There are codes to variously correct single b-bit errors and detect double b-bit errors. For G3 and G4, a code with 4-bit correction capability (S4EC) was implemented. Because the system design included dynamic on-line repair of chips with massive failures, it was not necessary to design a (78, 64) code which could both correct one 4-bit error and detect a second 4-bit error (D4ED). Such a code would have required an extra chip per checking block. The (76, 64) S4EC/DED ECC implemented on G3 and G4 is designed to ensure that all single-bit failures of one chip (and a very high probability of double- and triple-bit failures) occurring in the same doubleword as a 1 4-bit error on a second chip are detected [15]. G5 returns to single-bit-per-chip ECC and is therefore able to again use a less costly (72, 64) SEC/DED code and still protect the system from catastrophic failures caused by a single array-chip failure. ... snip ... and detailed 3090 description http://www.research.ibm.com/journal/sj/251/tucker.pdf ... from above Both the central expanded storages have error-correcting codes. The central storage has a single error-correcting, double-error-detecting code on each double word of data. The code is designed to detect all four-bit errors on a single card. The correcting code is passed to the caches on a fetch operation so that it can cover transmission errors as well as storage-array errors. The expanded storage is even more fault-tolerant. Each quad-word of the expanded storage has a double-error-correcting, triple-error-detecting code. Again, a four-bit error is always detected if caused by a single-card-level failure. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
