The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
recent posts mentioning doing dispatching in the 60s for improving both uniprocessor as well as multiprocessor cache hit ratios (including a form of low-overhead cache affinity dispatching) http://www.garlic.com/~lynn/2008c.html#78 CPU time differences for the same job http://www.garlic.com/~lynn/2008c.html#92 CPU time differences for the same job http://www.garlic.com/~lynn/2008c.html#81 Random thoughts http://www.garlic.com/~lynn/2008d.html#1 What happened to resumable instructions? last Friday with early mention of hiperdispatch http://www.garlic.com/~lynn/2008d.html#91 z10 presentation on 26 Feb there was some question of moving more of the multiprocessing dispatching function into the microcode ... or making it more sensitive to cache hit efficiencies ... or just fastpath software. i had done fastpath dispatch software as undergraduate in the 60s for cp67 (40yrs since it was announced at the spring 68 share meeting in houston). in the mid-70s ... doing work on 5-way multiprocessor product (which got canceled before shipping) ... misc past posts http://www.garlic.com/~lynn/subtopic.html#bounce ... i was able to move lots of stuff in microcode ... defining queued interface for path i/o operation as well as for dispatching (software and microcode interacting with common queue). the i/o stuff provided some of the function of 370-xa queued i/o interface ... the dispatching was somewhat analogous to what was defined later for the i432. re: http://www-01.ibm.com/common/ssi/cgi-bin/ssialias?infotype=AN&subtype=CA&htmlfid=897/ENUS108-154&appname=USN from above: HiperDispatch A z10 EC exclusive, HiperDispatch represents a cooperative effort between the z/OS operating system and the z10 EC hardware and is intended to provide improved efficiencies in both the hardware and the software in the following ways: * Work may be dispatched across fewer logical processors therefore reducing the multi-processor (MP) effects and lowering the interference among multiple partitions. * Specific z/OS tasks may be dispatched to a small subset of logical processors which Processor Resource/Systems Manager™ (PR/SM™) will tie to the same physical processors, thus improving the hardware cache re-use and locality of reference characteristics such as reducing the rate of cross-book communication. ... snip ... ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
