The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
[EMAIL PROTECTED] (Eric Bielefeld) writes: > I'm sorry to hear about that. As I've posted on this list before, I > went through the same thing from 2004 to 2006. P&H Mining got rid of > their MP3000, and replaced it with RS6000's. Those are i series, > right? Everything runs on SAP in a different state. They seem to be > happy with it. If you can get retraining, take it. There seems to be > a lot bigger job market in that area than z/OS. i & p series get a little confused. there was a project circa 1980 to replace the myriad of internal microprocessors with 801/risc processors ... misc. past references to 801, risc, romp, rios, power/pc, etc http://www.garlic.com/~lynn/subtopic.html#801 the microprocessor for as/400 (followon to s/38) was going to be 801 (iliad) and the microprocessor for 4341-followon was going to be 801 (iliad). many of the projects ran into problems ... and both the as/400 and 4341-following (4381) were redirected to risc processors. roll forward a decade ... rs/6000 rios was complex chipset (on my desk at moment is slightly green, clear plastic paper wap with six chips) that didn't have any support for cache consistency and smp support. a new project was started called somerset that was joint between ibm, motorola, apple, etc ... to do a single chip power/pc ... effectively with some cache consistency (smp support) from motorola (sort of adapted from motorola's 88000 risc processor). the executive we were reported to when we were doing ha/cmp product http://www.garlic.com/~lynn/subtopic.html#hacmp went over to head up somerset. the rochester group also got involved to do a flavor of power/pc that would finally replace the as/400 cisc microprocessor with an 801 risc (which was how as/400 was suppose to start out). there were little issues like most of the group was working on 64-bit address power/pc chip design ... while rochester was insisting on a 65-bit (as part of implementing some as/400 architecture feature). rs/6000s have had both (multi-chip) rios/power machines as well as single-chip (multiprocessor) power/pc chips. ... as an aside ... one of the reasons that we were doing ha/cmp scaleup; minor reference in this old post http://www.garlic.com/~lynn/95.html#13 and some (earlier) old email http://www.garlic.com/~lynn/lhwemail.html#medusa as "cluster" (loosely-coupled) ... was that was all there was with power/RIOS at the time ... not having support for cache consistency and tightly-coupled multiprocessor operations. over the years ... i & p series hardware continues to converge ... difference looking more and more like what sort of software was booted. POWER4 System Microarchitecture http://www-03.ibm.com/systems/p/hardware/whitepapers/power4.html from above: With POWER4, the convergence of iSeries and pSeries microprocessors will reach a new level. POWER4 was designed from the outset to satisfy the needs of both of these systems. ... snip ... -- 40+yrs virtualization experience (since Jan68), online at home since Mar70 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
