On 2/2/2021 4:21 AM, Binyamin Dissen wrote:
On Mon, 1 Feb 2021 13:45:45 +0000 Seymour J Metz<sme...@gmu.edu> wrote:
:>There's no reason to flush the cache, and doing so would be a major
performance hit. With luck there an IBM Systems Journal article or redbook on the
I-unit of current processors; if not, there should be.
How does the cache work?
Does MVS preserve the I-cache if a different thread is executing the same
address (or share the I-cache between different CPUs)?
Just to be clear, what he's talking about has nothing whatever to do wit
MVS or any other operating system. It's the IBM Z processor hardware
doing this...
Does it validate that the source of the cache is accessible whenever the SPKA
is issued, i.e., does the cache have key and fetch protect bits?
Any pre-executed instructions will have to be rolled back, correct?
Results of instruction fetch, instruction decode, address generation,
operand fetch, etc. down the "wrong" path are discarded.
--
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