Operand fetches and stores must appear to occur in proper order.
So is it saying that the machine obeys Rule 1? I will bet
dollars to donuts that that is not the case, that the machine
performs read operations before logically preceding write
operations, and that a program can be run to demonstrate that
that is the case.
...
Nothing is said about obeying Rule 3. The document does talk
about coherency, but the standard definition of cache coherence
is a weaker rule than MCWA.
...
When multiple instructions are executed concurrently the hardware will
ensure that the stores are completed in conceptual (not completion)
order. From the outside it must always appears as if the processor
executes instructions in order, though in reality it does not. That is
why they 'must appear' to occur in proper order. There are critical
sections of z/OS code (dispatcher intersect processing, for one) that
rely on this occurring. And if the hardware does not (and I saw it
happen 15 years ago on a non-IBM processor) interesting failures can occur).
The following are key items in the architecture with respect to this and
cache coherency-
1) Order of store completions, as viewed by other CPs. As defined in
the Principle of Operations, Chapter 5 - Program Execution, Sequence of
Storage References, Storage-operand References, Storage-Operand Store
References-
The CPU may delay placing results in storage. There is no defined
limit on the length of time that results may remain pending before they
are stored. This delay does not affect the sequence in which results
are placed in storage.
The results of one instruction are placed in storage after the results
of all preceding instructions have been placed in storage and before
any results of the succeeding instructions are stored, as observed by
other CPUs and by channel programs. The results of any one instruction
are stored in the sequence specified for that instruction.
2) Completion of all stores upon a fetch of data in the store queue. As
defined in Sequence of Storage References, Relation between Operand
Accesses-
As observed by other CPUs and by channel programs, storage-operand
fetches associated with one instruction execution appear to precede all
storage-operand references for conceptually subsequent instructions. A
storage-operand store specified by one instruction appears to precede
all storage-operand stores specified by conceptually subsequent
instructions, but it does not necessarily precede storage-operand
fetches specified by conceptually subsequent instructions. However, a
storage-operand store appears to precede a conceptually subsequent
storage-operand fetch from the same main-storage location.
3) The use of serializing instructions as appropriate. As defined in
Sequence of Storage References, Serialization, CPU Serialization-
All interruptions and the execution of certain instructions cause a
serialization of CPU operations. A serialization operation consists in
completing all conceptually previous storage accesses by the CPU, as
observed by other CPUs and by channel programs, before the conceptually
subsequent storage accesses occur. Serialization affects the sequence
of all CPU accesses to storage and to the storage keys, except for those
associated with ART-table-entry and DAT-table-entry fetching.
Greg
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