Rule 3 says there are events, some explicit (BCR 15,0) and some implicit
(interrupts), that force conceptual completion to occur, over and above
those required by rule number 1.
These rules are for storage consistency, especially between multiple
processors.
Registers are slightly different since each processors registers are
invisible to other CPUs. However when multiple instructions are
executed concurrently the hardware will ensure that the register stores
are completed in conceptual (not completion) order as well.
Greg
1) ...
The results of one instruction are placed in storage after the results
of all preceding instructions have been placed in storage and before
any results of the succeeding instructions are stored, as observed by
other CPUs and by channel programs. The results of any one instruction
are stored in the sequence specified for that instruction.
2) ...
3) ...
All interruptions and the execution of certain instructions cause a
serialization of CPU operations. A serialization operation consists in
completing all conceptually previous storage accesses by the CPU, as
observed by other CPUs and by channel programs, before the conceptually
subsequent storage accesses occur. Serialization affects the sequence
of all CPU accesses to storage and to the storage keys, except for those
associated with ART-table-entry and DAT-table-entry fetching.
What does rule 3 require that isn't equallly implied by rule 1? (Or did
I trim too much?)
What does this imply about register accesses? Does the STM early in
the FLIH observe register accesses "conceptually" serialized as storage
accesses are?
-- gil
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