>Yep, it is a bug.

>The PSW key mask has key 0 and key9  after the combination. Not key 8. I 
would
>not expect MODESET to alter the key mask.

No it is not a bug. The "expectation" is incorrect. The updating of the 
PKM is fully documented and is what we wanted it to be.

If you want to be switching keys, then why not simply be in supervisor 
state so that you can use SPKA without concern about the PKM?

MODESET MODE=SUP (maybe with KEY=ZERO)
... use SPKA as you will
MODESET MODE=PROB (maybe with KEY=NZERO)

I certainly have no objection to changing the documentation that currently 
has this:

The MODE parameter specifies whether bit 15 of the PSW is to be set to one 
or zero. When PSW bit 15 is one, the processor is in the problem state. 
For problem state, ...
 
to this:

The MODE parameter specifies whether bit 15 of the PSW is to be set to one 
or zero. 

When PSW bit 15 is one, the processor is in the problem state. For problem 
state, ...

This is the same wording, just not placing the "When" sentence in the same 
paragraph, since regardless of the MODE parameter, every PSW has a "bit 
15".

FWIW: MODESET long pre-dated the change of SPKA to be semi-privileged. 
Thus it was written "knowing" that SPKA would be done while in supervisor 
state (hence the MODE=SUP...MODE=PROB pairing). The introduction of 
semi-privileged SPKA coupled with the use of key=9 led to the desire to 
continue allowing the switching between the "current key" and "key=9" 
while in problem state. Other key switching could/should be done in 
supervisor state or, since you used the MODESET SVC to "switch from" then 
using the MODESET SVC to switch back. Could additional functionality have 
been provided to allow you to ask for a different set of rules when 
building the PKM? Sure. But changing the rules will never happen for 
compatibility reasons. And implementing additional rules will not happen 
unless there is sufficient business justifiation to cover the cost (and I 
am skeptical that such justification exists).

Peter Relson
z/OS Core Technology Design


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