Disabling for interruptions is not sufficient in a multi-processor world, right?
I don't pretend to be the world's biggest machine instruction expert. Am I reading the PoOp correctly that a task wishing another task's CSST to effectively appear to be entirely atomic (from its CPU's point of view) could achieve that effect by issuing a serialization instruction (BCR 15,0)? What about interrupts to the observing task? Suppose it were re-dispatched on a different CPU after the BCR and before observing storage? Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Steve Smith Sent: Tuesday, September 12, 2017 2:06 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: CSST question That is covered in Programming Note #5: "[CSST] should only be used when an interruption between the compare-and-swap operation and the store operation cannot be tolerated, and other means of disabling for interruptions are not practical." Per Programming Note #4, there's no other reason to use it: "The performance of [CSST] may be significantly slower than the that of separate [CS, BC, and ST] instructions." How such a situation develops, I don't know, but evidently it did somewhere. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
