Radoslaw Skorupka used lots of capital letters thusly: >Except ...it doesn't answer the question: HOW CPU >RECOGNIZE ITS OWN FAILURE?
I'll provide the same answer and expand on it briefly: "Nowadays, thanks to the wonders of microelectronic miniaturization, that's through intensive, thorough integrity checking at all critical instruction execution steps baked deep into every processor, and with tons of "transistor budget" spent on integrity checking and other RAS characteristics." Circuits checking circuits checking circuits.... Elardus Engelbrecht wrote: >Each CPU (on an IBM mainframe) consists of two halves. Both >halves are executing an instruction and the results are compared. Tom Marchant wrote: >This was documented in the announcement for the 9672 G5 models. Yes, but that was a long time ago. Twenty plus years ago, in fact. Time and technology have marched on. The precise implementation details are presumably trade secrets (that I'm fortunately not privy to), although you can refer to certain IBM technical publications, usually under the general heading of "RAS," to get some insight into the system design and its philosophy. I'll share a few words about the "two halves" approach that was a fine design but subject to considerable improvement and refinement, and then you can speculate and do your own research as you see fit. Perhaps some of you noticed that I used the words "defense in depth." Imagine for a moment that a particular processor error event occurred in a 9672 G5 machine. The instruction is redundantly executed in that machine's two identical units, results compared, the comparison fails, the instruction is retried, results compared again, and (let's assume) the results match and that dual hemispheric processor unit keeps humming along. (Or not, and then more stuff happens.) That worked and worked well.... But it's one line of defense. It's a great line of defense, but it's one line -- or something like one depending on how you count. Is there a newer, more sophisticated, higher performance, more efficient processor design that has multiple, layered lines of defense? That freely incorporates alternative "geometries," or "dimensionalities," beyond but not necessarily excluding "dual hemispherism"? That incorporates over 20 more years of field experience? Yes, there is. -------------------------------------------------------------------------------------------------------- Timothy Sipples IT Architect Executive, Industry Solutions, IBM Z & LinuxONE -------------------------------------------------------------------------------------------------------- E-Mail: sipp...@sg.ibm.com ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
