Em Qui, 2018-05-24 às 17:12 -0700, Paulo Zanoni escreveu:
> Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu:
> > From: James Ausmus <james.aus...@intel.com>
> >
> > Add support for DP_AUX_E. Here we also introduce the bits for the
> > AUX
> > power well E, however ICL power well support is still not enabled
> > yet,
> > so the power well is not used.
> >
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> > Signed-off-by: James Ausmus <james.aus...@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> > drivers/gpu/drm/i915/intel_display.h | 3 ++-
> > drivers/gpu/drm/i915/intel_dp.c | 7 +++++++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
> > 6 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index b86ed6401120..a85329f053dc 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1005,6 +1005,7 @@ enum modeset_restore {
> > #define DP_AUX_B 0x10
> > #define DP_AUX_C 0x20
> > #define DP_AUX_D 0x30
> > +#define DP_AUX_E 0x50
> > #define DP_AUX_F 0x60
> >
> > #define DDC_PIN_B 0x05
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 9f1b01ca4ed1..672bfaf2052a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2783,6 +2783,9 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > GEN9_AUX_CHANNEL_C |
> > GEN9_AUX_CHANNEL_D;
> >
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + tmp_mask |= ICL_AUX_CHANNEL_E;
> > +
> > if (IS_CNL_WITH_PORT_F(dev_priv) ||
> > INTEL_GEN(dev_priv) >= 11)
> > tmp_mask |= CNL_AUX_CHANNEL_F;
> > @@ -4168,6 +4171,9 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + de_port_masked |= ICL_AUX_CHANNEL_E;
> > +
> > if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >=
> > 11)
> > de_port_masked |= CNL_AUX_CHANNEL_F;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index ae7070c0806d..ba5285348534 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5342,6 +5342,13 @@ enum {
> > #define _DPD_AUX_CH_DATA4 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64320)
> > #define _DPD_AUX_CH_DATA5 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64324)
> >
> > +#define _DPE_AUX_CH_CTL (dev_priv-
> > > info.display_mmio_offset + 0x64410)
> >
> > +#define _DPE_AUX_CH_DATA1 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64414)
> > +#define _DPE_AUX_CH_DATA2 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64418)
> > +#define _DPE_AUX_CH_DATA3 (dev_priv-
> > >info.display_mmio_offset
> > + 0x6441c)
> > +#define _DPE_AUX_CH_DATA4 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64420)
> > +#define _DPE_AUX_CH_DATA5 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64424)
> > +
> > #define _DPF_AUX_CH_CTL (dev_priv-
> > > info.display_mmio_offset + 0x64510)
> >
> > #define _DPF_AUX_CH_DATA1 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64514)
> > #define _DPF_AUX_CH_DATA2 (dev_priv-
> > >info.display_mmio_offset
> > + 0x64518)
> > @@ -7040,6 +7047,7 @@ enum {
> > #define GEN8_DE_PORT_IMR _MMIO(0x44444)
> > #define GEN8_DE_PORT_IIR _MMIO(0x44448)
> > #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> > +#define ICL_AUX_CHANNEL_E (1 << 29)
> > #define CNL_AUX_CHANNEL_F (1 << 28)
> > #define GEN9_AUX_CHANNEL_D (1 << 27)
> > #define GEN9_AUX_CHANNEL_C (1 << 26)
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index fcedc600706b..653d85f8a374 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -162,7 +162,7 @@ enum aux_ch {
> > AUX_CH_B,
> > AUX_CH_C,
> > AUX_CH_D,
> > - _AUX_CH_E, /* does not exist */
> > + AUX_CH_E, /* ICL+ */
> > AUX_CH_F,
> > };
> >
> > @@ -203,6 +203,7 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_AUX_B,
> > POWER_DOMAIN_AUX_C,
> > POWER_DOMAIN_AUX_D,
> > + POWER_DOMAIN_AUX_E,
> > POWER_DOMAIN_AUX_F,
> > POWER_DOMAIN_AUX_IO_A,
> > POWER_DOMAIN_GMBUS,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index bcc3f330b301..588a5de3a8ee 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1527,6 +1527,9 @@ static enum aux_ch intel_aux_ch(struct
> > intel_dp
> > *intel_dp)
> > case DP_AUX_D:
> > aux_ch = AUX_CH_D;
> > break;
> > + case DP_AUX_E:
> > + aux_ch = AUX_CH_E;
> > + break;
> > case DP_AUX_F:
> > aux_ch = AUX_CH_F;
> > break;
> > @@ -1554,6 +1557,8 @@ intel_aux_power_domain(struct intel_dp
> > *intel_dp)
> > return POWER_DOMAIN_AUX_C;
> > case AUX_CH_D:
> > return POWER_DOMAIN_AUX_D;
> > + case AUX_CH_E:
> > + return POWER_DOMAIN_AUX_E;
> > case AUX_CH_F:
> > return POWER_DOMAIN_AUX_F;
> > default:
> > @@ -1640,6 +1645,7 @@ static i915_reg_t skl_aux_ctl_reg(struct
> > intel_dp *intel_dp)
> > case AUX_CH_B:
> > case AUX_CH_C:
> > case AUX_CH_D:
> > + case AUX_CH_E:
> > case AUX_CH_F:
> > return DP_AUX_CH_CTL(aux_ch);
> > default:
> > @@ -1658,6 +1664,7 @@ static i915_reg_t skl_aux_data_reg(struct
> > intel_dp *intel_dp, int index)
> > case AUX_CH_B:
> > case AUX_CH_C:
> > case AUX_CH_D:
> > + case AUX_CH_E:
> > case AUX_CH_F:
> > return DP_AUX_CH_DATA(aux_ch, index);
> > default:
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 53a6eaa9671a..0e4a631afc7d 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -128,6 +128,8 @@ intel_display_power_domain_str(enum
> > intel_display_power_domain domain)
> > return "AUX_C";
> > case POWER_DOMAIN_AUX_D:
> > return "AUX_D";
> > + case POWER_DOMAIN_AUX_E:
> > + return "AUX E";
>
> This should be "AUX_E" instead of "AUX E" and I'm 100% sure it's an
> error I introduced myself to the patch.
Just to clarify: this was a rebase issue due to changing the patch
order when sending upstream. The POWER_DOMAIN bits were part of the
patch that implements power wells for ICL, which we didn't submit yet.
I finally got to actually review this patch, so with that fixed:
Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> > case POWER_DOMAIN_AUX_F:
> > return "AUX_F";
> > case POWER_DOMAIN_AUX_IO_A:
>
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