On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
>
> ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> mapped to tc ports[1-4].
> This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> pin mapping table.
>
Fixes:?
> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> Cc: Madhav Chauhan <madhav.chau...@intel.com>
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_i2c.c | 12 ++++++------
> 3 files changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 452356a4af07..e48b717769b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3015,6 +3015,10 @@ enum i915_power_well_id {
> #define GPIOF _MMIO(0x5024)
> #define GPIOG _MMIO(0x5028)
> #define GPIOH _MMIO(0x502c)
> +#define GPIOJ _MMIO(0x5034)
I believe we could start using the real register name
instead the generic letter++, in order
to help all future readers to find it easily on spec.
like s/GPIOJ/GPIO_CTL_9 and etc...
The offset value already magically adds the 0xC0000
so offset as it is here doesn't help...
also leter J means nothing...
Anyways this might be on this patch or separated one
or just ignored, so:
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> +#define GPIOK _MMIO(0x5038)
> +#define GPIOL _MMIO(0x503C)
> +#define GPIOM _MMIO(0x5040)
> # define GPIO_CLOCK_DIR_MASK (1 << 0)
> # define GPIO_CLOCK_DIR_IN (0 << 1)
> # define GPIO_CLOCK_DIR_OUT (1 << 1)
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 75f02a0e7d39..3db2459c79b1 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2276,7 +2276,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
> *dev_priv,
> ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
> else if (HAS_PCH_CNP(dev_priv))
> ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> - else if (IS_ICELAKE(dev_priv))
> + else if (HAS_PCH_ICP(dev_priv))
> ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> else
> ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> b/drivers/gpu/drm/i915/intel_i2c.c
> index e6875509bcd9..b91e418028cb 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -77,12 +77,12 @@ static const struct gmbus_pin gmbus_pins_cnp[] = {
> };
>
> static const struct gmbus_pin gmbus_pins_icp[] = {
> - [GMBUS_PIN_1_BXT] = { "dpa", GPIOA },
> - [GMBUS_PIN_2_BXT] = { "dpb", GPIOB },
> - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOC },
> - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOD },
> - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOE },
> - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOF },
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> };
>
> /* pin is expected to be valid */
> --
> 2.14.3
>
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