On Thu, May 24, 2018 at 04:42:39PM -0700, Paulo Zanoni wrote:
> ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK
> table. Implement it just like CNL does.
>
> References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage
> on CNL")
> References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent
> voltage on CNL if required by DDI ports")
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 46
> +++++++++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> 2 files changed, 45 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 704ddb4d3ca7..642f1e542a62 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1861,11 +1861,35 @@ static void icl_set_cdclk(struct drm_i915_private
> *dev_priv,
> skl_cdclk_decimal(cdclk));
>
> mutex_lock(&dev_priv->pcu_lock);
> - /* TODO: add proper DVFS support. */
> - sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
> + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + cdclk_state->voltage_level);
> mutex_unlock(&dev_priv->pcu_lock);
>
> intel_update_cdclk(dev_priv);
> +
> + /*
> + * Can't read out the voltage level :(
> + * Let's just assume everything is as expected.
> + */
> + dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
> +}
> +
> +static u8 icl_calc_voltage_level(int cdclk)
> +{
> + switch (cdclk) {
> + case 50000:
> + case 307200:
> + case 312000:
> + return 0;
> + case 556800:
> + case 552000:
> + return 1;
> + default:
> + MISSING_CASE(cdclk);
> + case 652800:
> + case 648000:
> + return 2;
> + }
> }
>
> static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> @@ -1899,7 +1923,7 @@ static void icl_get_cdclk(struct drm_i915_private
> *dev_priv,
> */
> cdclk_state->vco = 0;
> cdclk_state->cdclk = cdclk_state->bypass;
> - return;
> + goto out;
> }
>
> cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
> @@ -1908,6 +1932,14 @@ static void icl_get_cdclk(struct drm_i915_private
> *dev_priv,
> WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
>
> cdclk_state->cdclk = cdclk_state->vco / 2;
> +
> +out:
> + /*
> + * Can't read this out :( Let's assume it's
> + * at least what the CDCLK frequency requires.
> + */
> + cdclk_state->voltage_level =
> + icl_calc_voltage_level(cdclk_state->cdclk);
> }
>
> /**
> @@ -1950,6 +1982,8 @@ void icl_init_cdclk(struct drm_i915_private *dev_priv)
> sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> sanitized_state.cdclk);
> + sanitized_state.voltage_level =
> + icl_calc_voltage_level(sanitized_state.cdclk);
>
> icl_set_cdclk(dev_priv, &sanitized_state);
> }
> @@ -1967,6 +2001,7 @@ void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> cdclk_state.cdclk = cdclk_state.bypass;
> cdclk_state.vco = 0;
> + cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
>
> icl_set_cdclk(dev_priv, &cdclk_state);
> }
> @@ -2470,6 +2505,9 @@ static int icl_modeset_calc_cdclk(struct
> drm_atomic_state *state)
>
> intel_state->cdclk.logical.vco = vco;
> intel_state->cdclk.logical.cdclk = cdclk;
> + intel_state->cdclk.logical.voltage_level =
> + max(icl_calc_voltage_level(cdclk),
> + cnl_compute_min_voltage_level(intel_state));
>
> if (!intel_state->active_crtcs) {
> cdclk = icl_calc_cdclk(0, ref);
> @@ -2477,6 +2515,8 @@ static int icl_modeset_calc_cdclk(struct
> drm_atomic_state *state)
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> + intel_state->cdclk.actual.voltage_level =
> + icl_calc_voltage_level(cdclk);
> } else {
> intel_state->cdclk.actual = intel_state->cdclk.logical;
> }
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 610c2d7d499c..6cdcbf9bf098 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3073,6 +3073,8 @@ void intel_ddi_compute_min_voltage_level(struct
> drm_i915_private *dev_priv,
> {
> if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
> crtc_state->min_voltage_level = 2;
> + else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
> + crtc_state->min_voltage_level = 1;
> }
>
> void intel_ddi_get_config(struct intel_encoder *encoder,
> --
> 2.14.3
>
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