[PATCH 007/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_3_IVB

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_3_IVB register macro.

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index d810a0bab901..a17c258bb219 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -366,7 +366,7 @@ static void ivb_pipe_crc_irq_handler(struct 
drm_i915_private *dev_priv,
        display_pipe_crc_irq_handler(dev_priv, pipe,
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
-                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_3_IVB(pipe)),
+                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_3_IVB(dev_priv, pipe)),
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_4_IVB(pipe)),
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_5_IVB(pipe)));
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7b7b9f73db02..248312e6e06e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1652,7 +1652,7 @@
 #define PIPE_CRC_CTL(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_CTL_A)
 #define PIPE_CRC_RES_1_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_1_A_IVB)
 #define PIPE_CRC_RES_2_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_2_A_IVB)
-#define PIPE_CRC_RES_3_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_3_A_IVB)
+#define PIPE_CRC_RES_3_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_3_A_IVB)
 #define PIPE_CRC_RES_4_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_4_A_IVB)
 #define PIPE_CRC_RES_5_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_5_A_IVB)
 
-- 
2.39.2