[PATCH 012/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_BLUE

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_BLUE register macro.

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 77be9f2029ac..5738e06a773c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -389,7 +389,7 @@ static void i9xx_pipe_crc_irq_handler(struct 
drm_i915_private *dev_priv,
        display_pipe_crc_irq_handler(dev_priv, pipe,
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_RED(dev_priv, pipe)),
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_GREEN(dev_priv, pipe)),
-                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_BLUE(pipe)),
+                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_BLUE(dev_priv, pipe)),
                                     res1, res2);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68a2dea9017b..b50115d1f1d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1658,7 +1658,7 @@
 
 #define PIPE_CRC_RES_RED(dev_priv, pipe)               _MMIO_TRANS2(dev_priv, 
pipe, _PIPE_CRC_RES_RED_A)
 #define PIPE_CRC_RES_GREEN(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_GREEN_A)
-#define PIPE_CRC_RES_BLUE(pipe)                _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_BLUE_A)
+#define PIPE_CRC_RES_BLUE(dev_priv, pipe)              _MMIO_TRANS2(dev_priv, 
pipe, _PIPE_CRC_RES_BLUE_A)
 #define PIPE_CRC_RES_RES1_I915(pipe)   _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_RES1_A_I915)
 #define PIPE_CRC_RES_RES2_G4X(pipe)    _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_RES2_A_G4X)
 
-- 
2.39.2