> -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of Ville > Syrjala > Sent: Wednesday, October 8, 2025 11:56 PM > To: [email protected] > Cc: [email protected] > Subject: [RFC][PATCH 03/11] drm/i915/cdclk: Add > intel_cdclk_min_cdclk_for_prefill() > > From: Ville Syrjälä <[email protected]> > > Introduce a helper to compute the min required cdclk frequency for a given > guardband size. This could be used to bump up the cdclk in case the vblank is > so > small that the normally computed minimum cdclk results in too slow a prefill.
Looks Good to me. Reviewed-by: Uma Shankar <[email protected]> > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ > drivers/gpu/drm/i915/display/intel_cdclk.h | 3 +++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 598593eafdf5..37515da056fe 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -4000,3 +4000,15 @@ unsigned int > intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state > > return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk); } > + > +int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state > *crtc_state, > + unsigned int prefill_lines_unadjusted, > + unsigned int prefill_lines_available) { > + struct intel_display *display = to_intel_display(crtc_state); > + const struct drm_display_mode *pipe_mode = &crtc_state- > >hw.pipe_mode; > + int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); > + > + return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, > prefill_lines_unadjusted), > + ppc * prefill_lines_available); > +} > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h > b/drivers/gpu/drm/i915/display/intel_cdclk.h > index d97f725a0160..b908ce2d9eb6 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h > @@ -72,5 +72,8 @@ void intel_cdclk_read_hw(struct intel_display *display); > unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state > *crtc_state, > const struct intel_cdclk_state > *cdclk_state); unsigned int intel_cdclk_prefill_adjustment_worst(const struct > intel_crtc_state *crtc_state); > +int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state > *crtc_state, > + unsigned int prefill_lines_unadjusted, > + unsigned int prefill_lines_available); > > #endif /* __INTEL_CDCLK_H__ */ > -- > 2.49.1
