On Wed, Oct 15, 2025 at 12:15:07AM -0300, Gustavo Sousa wrote: > From: Sai Teja Pottumuttu <[email protected]> > > On Xe3p_LPD, the dbuf blocks fields of different registers are now > documented as 13-bit fields. The dbuf isn't really large enough to need > the 13th bit, but let's go ahead and update the definition now just in > case some new display IP in future ends up needing the larger size. The > extra bit is an unused bit in previous display versions, so we can > safely just extend the existing definition. > > Bspec: 69847, 69880, 72053 > Signed-off-by: Sai Teja Pottumuttu <[email protected]> > Signed-off-by: Gustavo Sousa <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index ca9fdfbbe57c..479bb3f7f92b 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -324,7 +324,7 @@ > #define PLANE_WM_IGNORE_LINES REG_BIT(30) > #define PLANE_WM_AUTO_MIN_ALLOC_EN REG_BIT(29) > #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) > -#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) > +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(12, 0) > > #define _PLANE_WM_SAGV_1_A 0x70258 > #define _PLANE_WM_SAGV_1_B 0x71258 > @@ -375,10 +375,10 @@ > _PLANE_BUF_CFG_1_A, > _PLANE_BUF_CFG_1_B, \ > _PLANE_BUF_CFG_2_A, > _PLANE_BUF_CFG_2_B) > > -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ > -#define PLANE_BUF_END_MASK REG_GENMASK(27, 16) > +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3p_lpd 13 bits */ > +#define PLANE_BUF_END_MASK REG_GENMASK(28, 16) > #define PLANE_BUF_END(end) > REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) > -#define PLANE_BUF_START_MASK REG_GENMASK(11, 0) > +#define PLANE_BUF_START_MASK REG_GENMASK(12, 0) > #define PLANE_BUF_START(start) > REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) > > #define _PLANE_MIN_BUF_CFG_1_A 0x70274 > @@ -389,9 +389,9 @@ > _PLANE_MIN_BUF_CFG_1_A, > _PLANE_MIN_BUF_CFG_1_B, \ > _PLANE_MIN_BUF_CFG_2_A, > _PLANE_MIN_BUF_CFG_2_B) > #define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31) > -#define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(27, 16) > +#define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(28, 16) > #define PLANE_MIN_DBUF_BLOCKS(val) > REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val)) > -#define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(11, 0) > +#define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(12, 0) > #define PLANE_INTERIM_DBUF_BLOCKS(val) > REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val)) > > /* tgl+ */ > > -- > 2.51.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
