Quoting Jani Nikula (2025-10-15 12:00:51-03:00)
>On Wed, 15 Oct 2025, Gustavo Sousa <[email protected]> wrote:
>> From: Jouni Högander <[email protected]>
>>
>> Ensure the minimum selective update line count is 4 in case of display
>> version 35 and onwards.
>>
>> Bspec: 69887
>> Signed-off-by: Jouni Högander <[email protected]>
>> Signed-off-by: Gustavo Sousa <[email protected]>
>> ---
>> drivers/gpu/drm/i915/display/intel_psr.c | 25 +++++++++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 2131473cead6..c663ca91f490 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -2701,6 +2701,29 @@ intel_psr_apply_su_area_workarounds(struct
>> intel_crtc_state *crtc_state)
>> intel_psr_apply_pr_link_on_su_wa(crtc_state);
>> }
>>
>> +static void intel_psr_su_area_min_lines(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_display *display = to_intel_display(crtc_state);
>> + struct drm_rect damaged_area;
>> +
>> + /*
>> + * Bspec mentions 4 being minimum lines in SU for display version
>> + * 35 and onwards.
>> + */
>> + if (DISPLAY_VER(display) < 35 ||
>> drm_rect_height(&crtc_state->psr2_su_area) >= 4)
>> + return;
>> +
>> + damaged_area.x1 = crtc_state->psr2_su_area.x1;
>> + damaged_area.y1 = crtc_state->psr2_su_area.y1;
>> + damaged_area.x2 = crtc_state->psr2_su_area.x2;
>> + damaged_area.y2 = crtc_state->psr2_su_area.y2;
>> +
>> + damaged_area.y2 += 4 - drm_rect_height(&damaged_area);
>> + drm_rect_intersect(&damaged_area, &crtc_state->pipe_src);
>> + damaged_area.y1 -= 4 - drm_rect_height(&damaged_area);
>
>Stray extra spaces in there.
Huh... Interesting that I did not catch this in checkpatch output.
Thanks for noticing.
--
Gustavo Sousa
>
>> + clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
>> &crtc_state->pipe_src);
>> +}
>> +
>> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>> struct intel_crtc *crtc)
>> {
>> @@ -2809,6 +2832,8 @@ int intel_psr2_sel_fetch_update(struct
>> intel_atomic_state *state,
>> if (full_update)
>> goto skip_sel_fetch_set_loop;
>>
>> + intel_psr_su_area_min_lines(crtc_state);
>> +
>> intel_psr_apply_su_area_workarounds(crtc_state);
>>
>> ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
>
>--
>Jani Nikula, Intel
