On 11/3/2025 10:59 AM, Mitul Golani wrote:
Configure DC Balance Flipline adjustment once after other
DC balance adjustment registers are written.
Bspec: 68935
Signed-off-by: Mitul Golani <[email protected]>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2d418f45569f..97949ff782aa 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -785,6 +785,8 @@ static void intel_vrr_tg_enable(const struct
intel_crtc_state *crtc_state,
VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
intel_de_write(display,
TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline -
1));
+ intel_de_write(display,
TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+ VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline -
1));
This can be part of the earlier patch.
Regards,
Ankit
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
crtc_state->vrr.dc_balance.vmin - 1);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
