On 11/3/2025 10:59 AM, Mitul Golani wrote:
After VRR Push is sent, need to wait till flipline decision boundary
to get Push bit to get cleared.
Signed-off-by: Mitul Golani <[email protected]>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b256517d58cf..faec325e7652 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7287,6 +7287,22 @@ static void intel_atomic_dsb_prepare(struct
intel_atomic_state *state,
intel_color_prepare_commit(state, crtc);
}
+static int
+dcb_vmin_vblank_start(struct intel_crtc_state *crtc_state)
+{
+ return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
+ intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
+ intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+}
+
+static int
+dcb_vmax_vblank_start(struct intel_crtc_state *crtc_state)
+{
+ return (intel_vrr_dcb_vmax_vblank_start_next(crtc_state) < 0) ?
+ intel_vrr_dcb_vmax_vblank_start_final(crtc_state) :
+ intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+}
+
static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -7371,6 +7387,13 @@ static void intel_atomic_dsb_finish(struct
intel_atomic_state *state,
intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
intel_dsb_wait_for_delayed_vblank(state,
new_crtc_state->dsb_commit);
+
+ if (new_crtc_state->vrr.dc_balance.enable) {
+ intel_dsb_wait_scanline_in(state,
new_crtc_state->dsb_commit,
+
dcb_vmin_vblank_start(new_crtc_state),
+
dcb_vmax_vblank_start(new_crtc_state));
+ }
Hmm... lets not add this as a separate thing. The idea is to wait for
vmin safe window, so that after that we are exactly SCL lines away from
the delayed vblank.
As I understand, DMC FW will adjust the VRR timings so we need to use
the Live values from the registers.
I think we need to use the TRANS_VRR_DCB_FLIPLINE_LIVE value for
computing thevrr vmin safe window end in
intel_dsb_wait_for_delayed_vblank() when DC balancing is enabled.
Regards,
Ankit
+
intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
new_crtc_state);
intel_dsb_interrupt(new_crtc_state->dsb_commit);
