> Subject: [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup > > From: Imre Deak <[email protected]> > > Define the C10 PLL SSC register range via macros, so the HW/SW state of these > register can be verified by a follow-up change, reusing these macros. > > Signed-off-by: Imre Deak <[email protected]> > Signed-off-by: Mika Kahola <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index cc5aa38c3364..b394b0397d62 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2064,6 +2064,9 @@ static void intel_cx0pll_update_ssc(struct > intel_encoder *encoder, > } > } > > +#define C10_PLL_SSC_REG_START_IDX 4 > +#define C10_PLL_SSC_REG_COUNT 5 > + > static void intel_c10pll_update_pll(struct intel_encoder *encoder, > struct intel_cx0pll_state *pll_state) { @@ > - > 2073,8 +2076,11 @@ static void intel_c10pll_update_pll(struct intel_encoder > *encoder, > if (pll_state->ssc_enabled) > return; > > - drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); > - for (i = 4; i < 9; i++) > + drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < > + C10_PLL_SSC_REG_START_IDX + > C10_PLL_SSC_REG_COUNT); > + for (i = C10_PLL_SSC_REG_START_IDX; > + i < C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT; > + i++) > pll_state->c10.pll[i] = 0; > } > > -- > 2.34.1
