> Subject: [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock from PLL > state > > From: Imre Deak <[email protected]> > > The port clock is tracked in the PLL state, so there is no need to pass it > separately to __intel_cx0pll_enable(). Drop the port clock function param > accordingly. > > Signed-off-by: Imre Deak <[email protected]> > Signed-off-by: Mika Kahola <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 +++++------------ > 1 file changed, 5 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index f1216beb5581..29bcfe8fb6f5 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -3206,10 +3206,10 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 > lane_mask) > return val; > } > > -static void __intel_cx0pll_enable(struct intel_encoder *encoder, > - const struct intel_cx0pll_state *pll_state, > - int port_clock) > +static void intel_cx0pll_enable(struct intel_encoder *encoder, > + const struct intel_cx0pll_state *pll_state) > { > + int port_clock = pll_state->use_c10 ? pll_state->c10.clock : > +pll_state->c20.clock; > struct intel_display *display = to_intel_display(encoder); > enum phy phy = intel_encoder_to_phy(encoder); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ - > 3288,13 +3288,6 @@ static void __intel_cx0pll_enable(struct intel_encoder > *encoder, > intel_cx0_phy_transaction_end(encoder, wakeref); } > > -static void intel_cx0pll_enable(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll, > - crtc_state->port_clock); > -} > - > int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) { > struct intel_display *display = to_intel_display(encoder); @@ -3424,7 > +3417,7 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder, > if (intel_tc_port_in_tbt_alt_mode(dig_port)) > intel_mtl_tbt_pll_enable(encoder, crtc_state); > else > - intel_cx0pll_enable(encoder, crtc_state); > + intel_cx0pll_enable(encoder, &crtc_state- > >dpll_hw_state.cx0pll); > } > > /* > @@ -3847,7 +3840,7 @@ void intel_cx0_pll_power_save_wa(struct > intel_display *display) > "[ENCODER:%d:%s] Applying power saving > workaround on disabled PLL\n", > encoder->base.base.id, encoder->base.name); > > - __intel_cx0pll_enable(encoder, &pll_state, port_clock); > + intel_cx0pll_enable(encoder, &pll_state); > intel_cx0pll_disable(encoder); > } > } > -- > 2.34.1
