> -----Original Message----- > From: Deak, Imre <[email protected]> > Sent: Tuesday, November 11, 2025 3:42 PM > To: Kandpal, Suraj <[email protected]> > Cc: Kahola, Mika <[email protected]>; [email protected]; > [email protected] > Subject: Re: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL > state > > On Tue, Nov 11, 2025 at 08:08:34AM +0200, Suraj Kandpal wrote: > > [...] > > > @@ -2929,10 +2958,11 @@ static void intel_c20_pll_program(struct > > > intel_display *display, > > > > > > static void intel_program_port_clock_ctl(struct intel_encoder *encoder, > > > const struct intel_cx0pll_state > *pll_state, > > > - bool is_dp, int port_clock, > > > + int port_clock, > > > bool lane_reversal) > > > { > > > struct intel_display *display = to_intel_display(encoder); > > > + bool is_dp = cx0pll_state_is_dp(pll_state); > > > > Wouldn't a simple check of drm_encoder's type tell us if it is dp or not ? > > For a DDI encoder drm_encoder::encoder_type is > DRM_MODE_ENCODER_TMDS, from which you can't determine if the encoder is > used for a DP or HDMI output. This also applies to intel_encoder_is_dp(), > which > will return true if for instance a DDI encoder wired to a DP++ connector is > used > for an HDMI output. > In that case LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > > Regards, > > Suraj Kandpal
- RE: [CI 10/32] drm/i915/display: Read out the Cx0 PHY ... Kandpal, Suraj
- [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC regis... Mika Kahola
- RE: [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL ... Kandpal, Suraj
- [CI 07/32] drm/i915/display: Add macro to get DDI port widt... Mika Kahola
- RE: [CI 07/32] drm/i915/display: Add macro to get DDI ... Kandpal, Suraj
- [CI 15/32] drm/i915/display: Remove state verification Mika Kahola
- RE: [CI 15/32] drm/i915/display: Remove state verifica... Kandpal, Suraj
- [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from... Mika Kahola
- RE: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP ... Kandpal, Suraj
- Re: [CI 11/32] drm/i915/display: Determine Cx0 PLL... Imre Deak
- RE: [CI 11/32] drm/i915/display: Determine Cx0... Kandpal, Suraj
- [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock f... Mika Kahola
- RE: [CI 12/32] drm/i915/display: Determine Cx0 PLL por... Kandpal, Suraj
- [CI 17/32] drm/i915/display: Update C10/C20 state calculati... Mika Kahola
- RE: [CI 17/32] drm/i915/display: Update C10/C20 state ... Kandpal, Suraj
- [CI 16/32] drm/i915/display: PLL information for MTL+ Mika Kahola
- RE: [CI 16/32] drm/i915/display: PLL information for M... Kandpal, Suraj
- [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane... Mika Kahola
- RE: [CI 08/32] drm/i915/display: Track the Cx0 PHY ena... Kandpal, Suraj
- [CI 19/32] drm/i915/display: MTL+ .get_dplls Mika Kahola
