On Mon, 17 Nov 2025, Animesh Manna <[email protected]> wrote:
> Timing registers are separate for CMTG, read transcoder register
> and program cmtg transcoder with those values.
>
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 13 ++++++++
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> 4 files changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 4640cafe8dde..5e9aaa50b38f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -208,3 +208,34 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> if (clk_sel_set)
> intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> +
> +static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> + intel_de_read(display, TRANS_HTOTAL(display,
> cpu_transcoder)));
> + intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> + intel_de_read(display, TRANS_HBLANK(display,
> cpu_transcoder)));
> + intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> + intel_de_read(display, TRANS_HSYNC(display,
> cpu_transcoder)));
> + intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> + intel_de_read(display, TRANS_VTOTAL(display,
> cpu_transcoder)));
> + intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> + intel_de_read(display, TRANS_VBLANK(display,
> cpu_transcoder)));
> + intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> + intel_de_read(display, TRANS_VSYNC(display,
> cpu_transcoder)));
If something needs to be written in multiple places, it needs to be
written from the same source software state, not via hardware like this.
> +}
> +
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
> +{
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
> + return;
> +
> + /* Program CMTG Transcoder Timings */
Is this comment helpful?
> + intel_cmtg_set_timings(crtc_state);
> +
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index bef2426b2787..113042e5d3a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,5 +11,6 @@ struct intel_crtc_state;
>
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 9fd54f7e9d1f..47403bbcac7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -8,6 +8,12 @@
>
> #include "intel_display_reg_defs.h"
>
> +enum cmtg {
> + CMTG_A = 0,
> + CMTG_B,
> + MAX_CMTG
> +};
> +
> #define CMTG_CLK_SEL _MMIO(0x46160)
> #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
> #define CMTG_CLK_SELECT_PHYA_ENABLE 0x4
> @@ -20,4 +26,11 @@
> #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
> #define CMTG_ENABLE REG_BIT(31)
>
> +#define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) * 0x100)
> +#define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) * 0x100)
> +#define TRANS_HSYNC_CMTG(id) _MMIO(0x6F008 + (id) * 0x100)
> +#define TRANS_VTOTAL_CMTG(id) _MMIO(0x6F00C + (id) * 0x100)
> +#define TRANS_VBLANK_CMTG(id) _MMIO(0x6F010 + (id) * 0x100)
> +#define TRANS_VSYNC_CMTG(id) _MMIO(0x6F014 + (id) * 0x100)
> +
> #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 069967114bd9..19242c12f52a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -63,6 +63,7 @@
> #include "intel_casf.h"
> #include "intel_cdclk.h"
> #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
> #include "intel_color.h"
> #include "intel_crt.h"
> #include "intel_crtc.h"
> @@ -1669,6 +1670,9 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
> if (!transcoder_is_dsi(cpu_transcoder))
> hsw_configure_cpu_transcoder(new_crtc_state);
>
> + if (new_crtc_state->enable_cmtg)
> + intel_cmtg_enable(new_crtc_state);
> +
> for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state,
> i) {
> const struct intel_crtc_state *pipe_crtc_state =
> intel_atomic_get_new_crtc_state(state, pipe_crtc);
--
Jani Nikula, Intel
