On Mon, 17 Nov 2025, Animesh Manna <[email protected]> wrote:
> Program CMTG Clk Select.
>
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 22 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h | 2 ++
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 +++++--
> 4 files changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 165138b95cb2..4640cafe8dde 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG)
> @@ -186,3 +187,24 @@ void intel_cmtg_sanitize(struct intel_display *display)
>
> intel_cmtg_disable(display, &cmtg_config);
> }
> +
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 clk_sel_clr = 0;
> + u32 clk_sel_set = 0;
> +
> + if (cpu_transcoder == TRANSCODER_A) {
> + clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> + clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> + }
> +
> + if (cpu_transcoder == TRANSCODER_B) {
> + clk_sel_clr = CMTG_CLK_SEL_A_MASK;
SEL_A for both?
> + clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> + }
> +
> + if (clk_sel_set)
What if needs to be disabled? I don't get it.
> + intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..bef2426b2787 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -7,7 +7,9 @@
> #define __INTEL_CMTG_H__
>
> struct intel_display;
> +struct intel_crtc_state;
>
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
>
> #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 945a35578284..9fd54f7e9d1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -10,8 +10,10 @@
>
> #define CMTG_CLK_SEL _MMIO(0x46160)
> #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
> +#define CMTG_CLK_SELECT_PHYA_ENABLE 0x4
> #define CMTG_CLK_SEL_A_DISABLED
> REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
> #define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13)
> +#define CMTG_CLK_SELECT_PHYB_ENABLE 0x6
> #define CMTG_CLK_SEL_B_DISABLED
> REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
>
> #define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index d98b4cf6b60e..32969985d6f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_print.h>
>
> #include "intel_alpm.h"
> +#include "intel_cmtg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_ddi.h"
> @@ -3209,10 +3210,13 @@ void intel_mtl_pll_enable(struct intel_encoder
> *encoder,
> {
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>
> - if (intel_tc_port_in_tbt_alt_mode(dig_port))
> + if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
> intel_mtl_tbt_pll_enable(encoder, crtc_state);
> - else
> + } else {
> intel_cx0pll_enable(encoder, crtc_state);
> + if (crtc_state->enable_cmtg)
> + intel_cmtg_set_clk_select(crtc_state);
> + }
> }
>
> /*
--
Jani Nikula, Intel
