The encoder state computation should use the drm_display_mode::crtc_clock member, instead of the clock member, the former one possibly having a necessary adjustment wrt. to the latter due to driver specific constraints. In practice the two values should not differ at spots changed in this patch, since only MSO and 3D modes would make them different, neither MSO or 3D relevant here, but still use the expected crtc_clock version for consistency.
Signed-off-by: Imre Deak <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index beda340d05923..d70cb35cf68bc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2050,7 +2050,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, continue; } else { if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, - lane_count, adjusted_mode->clock, + lane_count, + adjusted_mode->crtc_clock, pipe_config->output_format, timeslots)) continue; @@ -2211,7 +2212,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16; int ret; - dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, + dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->crtc_clock, adjusted_mode->hdisplay, num_joined_pipes); max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16); -- 2.49.1
