On Thu, 2025-11-27 at 19:49 +0200, Imre Deak wrote: > Factor out intel_dp_link_bw_overhead(), used later for BW calculation > during DP SST mode validation and state computation. > > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 26 +++++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++++------------ > 3 files changed, 34 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index d70cb35cf68bc..4722ee26b1181 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -424,6 +424,32 @@ static int intel_dp_min_lane_count(struct intel_dp > *intel_dp) > return 1; > } > > +int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, > + int dsc_slice_count, int bpp_x16, unsigned long > flags) > +{ > + int overhead; > + > + WARN_ON(flags & ~(DRM_DP_BW_OVERHEAD_MST | > DRM_DP_BW_OVERHEAD_SSC_REF_CLK | > + DRM_DP_BW_OVERHEAD_FEC)); > + > + if (drm_dp_is_uhbr_rate(link_clock)) > + flags |= DRM_DP_BW_OVERHEAD_UHBR; > + > + if (dsc_slice_count) > + flags |= DRM_DP_BW_OVERHEAD_DSC; > + > + overhead = drm_dp_bw_overhead(lane_count, hdisplay, > + dsc_slice_count, > + bpp_x16, > + flags); > + > + /* > + * TODO: clarify whether a minimum required by the fixed FEC overhead > + * in the bspec audio programming sequence is required here. > + */ > + return max(overhead, intel_dp_bw_fec_overhead(flags & > DRM_DP_BW_OVERHEAD_FEC)); > +} > + > /* > * The required data bandwidth for a mode with given pixel clock and bpp. > This > * is the required net bandwidth independent of the data bandwidth > efficiency. > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index 97e361458f760..d7f9410129f49 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -117,6 +117,8 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int > port_clock, > bool intel_dp_source_supports_tps3(struct intel_display *display); > bool intel_dp_source_supports_tps4(struct intel_display *display); > > +int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, > + int dsc_slice_count, int bpp_x16, unsigned long > flags); > int intel_dp_link_required(int pixel_clock, int bpp); > int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, > int bw_overhead); > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 1a4784f0cd6bd..c1058b4a85d02 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -180,26 +180,16 @@ static int intel_dp_mst_bw_overhead(const struct > intel_crtc_state *crtc_state, > const struct drm_display_mode *adjusted_mode = > &crtc_state->hw.adjusted_mode; > unsigned long flags = DRM_DP_BW_OVERHEAD_MST; > - int overhead; > > - flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0; > flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; > flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; > > - if (dsc_slice_count) > - flags |= DRM_DP_BW_OVERHEAD_DSC; > - > - overhead = drm_dp_bw_overhead(crtc_state->lane_count, > - adjusted_mode->hdisplay, > - dsc_slice_count, > - bpp_x16, > - flags); > - > - /* > - * TODO: clarify whether a minimum required by the fixed FEC overhead > - * in the bspec audio programming sequence is required here. > - */ > - return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable)); > + return intel_dp_link_bw_overhead(crtc_state->port_clock, > + crtc_state->lane_count, > + adjusted_mode->hdisplay, > + dsc_slice_count, > + bpp_x16, > + flags); > } > > static void intel_dp_mst_compute_m_n(const struct intel_crtc_state > *crtc_state,
Reviewed-by: Luca Coelho <[email protected]> -- Cheers, Luca.
