On Thu, 2025-11-27 at 19:50 +0200, Imre Deak wrote: > Add intel_dp_mode_valid_with_dsc() and call this for an SST/MST mode > validation to prepare for a follow-up change using a way to verify > the > mode's required BW the same way this is done elsewhere during state > computation (which in turn depends on the mode's effective data rate > with the corresponding BW overhead). > > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 57 +++++++++++++++---- > -- > drivers/gpu/drm/i915/display/intel_dp.h | 7 +++ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 29 ++++------- > 3 files changed, 57 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 9deb99eda8813..b40edf4febcb7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1579,24 +1579,20 @@ intel_dp_mode_valid(struct drm_connector > *_connector, > dsc_slice_count = > drm_dp_dsc_sink_max_slice_count(conn > ector->dp.dsc_dpcd, > true > ); > + dsc = dsc_max_compressed_bpp && > dsc_slice_count; > } else if (drm_dp_sink_supports_fec(connector- > >dp.fec_capability)) { > - dsc_max_compressed_bpp = > - > intel_dp_dsc_get_max_compressed_bpp(display, > - > max_link_clock, > - > max_lanes, > - > target_clock, > - > mode->hdisplay, > - > num_joined_pipes, > - > output_format, > - > pipe_bpp, 64); > - dsc_slice_count = > - > intel_dp_dsc_get_slice_count(connector, > - > target_clock, > - mode- > >hdisplay, > - > num_joined_pipes); > + unsigned long bw_overhead_flags = 0; > + > + if (!drm_dp_is_uhbr_rate(max_link_clock)) > + bw_overhead_flags |= > DRM_DP_BW_OVERHEAD_FEC; > + > + dsc = > intel_dp_mode_valid_with_dsc(connector, > + > max_link_clock, max_lanes, > + > target_clock, mode->hdisplay, > + > num_joined_pipes, > + > output_format, pipe_bpp, > + > bw_overhead_flags); > } > - > - dsc = dsc_max_compressed_bpp && dsc_slice_count; > } > > if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && > !dsc) > @@ -2704,6 +2700,35 @@ static int > compute_max_compressed_bpp_x16(struct intel_connector *connector, > return max_link_bpp_x16; > } > > +bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, > + int link_clock, int lane_count, > + int mode_clock, int mode_hdisplay, > + int num_joined_pipes, > + enum intel_output_format > output_format, > + int pipe_bpp, unsigned long > bw_overhead_flags)
bw_overhead_flags is not used in this patch. But I see that this is being used in the next patch. Reviewed-by: Vinod Govindapillai <[email protected]> > +{ > + struct intel_display *display = to_intel_display(connector); > + int dsc_max_compressed_bpp; > + int dsc_slice_count; > + > + dsc_max_compressed_bpp = > + intel_dp_dsc_get_max_compressed_bpp(display, > + link_clock, > + lane_count, > + mode_clock, > + mode_hdisplay, > + > num_joined_pipes, > + output_format, > + pipe_bpp, 64); > + dsc_slice_count = > + intel_dp_dsc_get_slice_count(connector, > + mode_clock, > + mode_hdisplay, > + num_joined_pipes); > + > + return dsc_max_compressed_bpp && dsc_slice_count; > +} > + > /* > * Calculate the output link min, max bpp values in limits based on > the pipe bpp > * range, crtc_state and dsc mode. Return true on success. > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index 489b8c945da39..0ec7baec7a8e8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -150,6 +150,13 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct > intel_display *display, > enum intel_output_format > output_format, > u32 pipe_bpp, > u32 timeslots); > + > +bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, > + int link_clock, int lane_count, > + int mode_clock, int mode_hdisplay, > + int num_joined_pipes, > + enum intel_output_format > output_format, > + int pipe_bpp, unsigned long > bw_overhead_flags); > bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, > int bpp_x16); > u8 intel_dp_dsc_get_slice_count(const struct intel_connector > *connector, > int mode_clock, int mode_hdisplay, > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 0db6ed2d9664c..e3f8679e95252 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -1462,8 +1462,6 @@ mst_connector_mode_valid_ctx(struct > drm_connector *_connector, > DRM_DP_BW_OVERHEAD_MST | > DRM_DP_BW_OVERHEAD_SSC_REF_CLK; > int ret; > bool dsc = false; > - u16 dsc_max_compressed_bpp = 0; > - u8 dsc_slice_count = 0; > int target_clock = mode->clock; > int num_joined_pipes; > > @@ -1522,31 +1520,22 @@ mst_connector_mode_valid_ctx(struct > drm_connector *_connector, > return 0; > } > > - if (intel_dp_has_dsc(connector)) { > + if (intel_dp_has_dsc(connector) && > drm_dp_sink_supports_fec(connector->dp.fec_capability)) { > /* > * TBD pass the connector BPC, > * for now U8_MAX so that max BPC on that platform > would be picked > */ > int pipe_bpp = > intel_dp_dsc_compute_max_bpp(connector, U8_MAX); > > - if (drm_dp_sink_supports_fec(connector- > >dp.fec_capability)) { > - dsc_max_compressed_bpp = > - > intel_dp_dsc_get_max_compressed_bpp(display, > - > max_link_clock, > - > max_lanes, > - > target_clock, > - > mode->hdisplay, > - > num_joined_pipes, > - > INTEL_OUTPUT_FORMAT_RGB, > - > pipe_bpp, 64); > - dsc_slice_count = > - > intel_dp_dsc_get_slice_count(connector, > - > target_clock, > - mode- > >hdisplay, > - > num_joined_pipes); > - } > + if (!drm_dp_is_uhbr_rate(max_link_clock)) > + bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC; > > - dsc = dsc_max_compressed_bpp && dsc_slice_count; > + dsc = intel_dp_mode_valid_with_dsc(connector, > + max_link_clock, > max_lanes, > + target_clock, > mode->hdisplay, > + num_joined_pipes, > + > INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, > + > bw_overhead_flags); > } > > if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && > !dsc) {
