Move GEN9_CLKGATE_DIS_0 reg to common header to make intel_modeset_setup.c free from i915_reg.h include.
Signed-off-by: Uma Shankar <[email protected]> --- drivers/gpu/drm/i915/display/intel_modeset_setup.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 13 ------------- include/drm/intel/intel_gmd_common_regs.h | 13 +++++++++++++ 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index d10cbf69a5f8..2502f0076e64 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -10,8 +10,8 @@ #include <drm/drm_atomic_uapi.h> #include <drm/drm_print.h> #include <drm/drm_vblank.h> +#include <drm/intel/intel_gmd_common_regs.h> -#include "i915_reg.h" #include "i9xx_wm.h" #include "intel_atomic.h" #include "intel_bw.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 44df40e25e37..e41b80cae1d8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -632,19 +632,6 @@ #define VLV_CLK_CTL2 _MMIO(0x101104) #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 -/* - * GEN9 clock gating regs - */ -#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) -#define DARBF_GATING_DIS REG_BIT(27) -#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe)) -#define PWM2_GATING_DIS REG_BIT(14) -#define PWM1_GATING_DIS REG_BIT(13) - -#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) -#define TGL_VRH_GATING_DIS REG_BIT(31) -#define DPT_GATING_DIS REG_BIT(22) - #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) #define PIPEB_HLINE_INT_EN REG_BIT(28) diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h index 5a42b473de8a..6faccce3de2a 100644 --- a/include/drm/intel/intel_gmd_common_regs.h +++ b/include/drm/intel/intel_gmd_common_regs.h @@ -403,4 +403,17 @@ #define GEN11_GT_DW1_IRQ (1 << 1) #define GEN11_GT_DW0_IRQ (1 << 0) +/* + * GEN9 clock gating regs + */ +#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) +#define DARBF_GATING_DIS REG_BIT(27) +#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe)) +#define PWM2_GATING_DIS REG_BIT(14) +#define PWM1_GATING_DIS REG_BIT(13) + +#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) +#define TGL_VRH_GATING_DIS REG_BIT(31) +#define DPT_GATING_DIS REG_BIT(22) + #endif -- 2.50.1
