Make intel_rom.c free from including i915_reg.h.

Signed-off-by: Uma Shankar <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_rom.c  | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h           | 8 --------
 include/drm/intel/intel_gmd_common_regs.h | 8 ++++++++
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_rom.c 
b/drivers/gpu/drm/i915/display/intel_rom.c
index 2f17dc856e7f..2b9801d370a3 100644
--- a/drivers/gpu/drm/i915/display/intel_rom.c
+++ b/drivers/gpu/drm/i915/display/intel_rom.c
@@ -3,9 +3,9 @@
  * Copyright © 2024 Intel Corporation
  */
 
-#include "i915_drv.h"
-#include "i915_reg.h"
+#include <drm/intel/intel_gmd_common_regs.h>
 
+#include "i915_drv.h"
 #include "intel_rom.h"
 #include "intel_uncore.h"
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77ae9a9ba27a..fd3f87f0bcd9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -891,14 +891,6 @@
 #define   SGGI_DIS                     REG_BIT(15)
 #define   SGR_DIS                      REG_BIT(13)
 
-#define PRIMARY_SPI_TRIGGER                    _MMIO(0x102040)
-#define PRIMARY_SPI_ADDRESS                    _MMIO(0x102080)
-#define PRIMARY_SPI_REGIONID                   _MMIO(0x102084)
-#define SPI_STATIC_REGIONS                     _MMIO(0x102090)
-#define   OPTIONROM_SPI_REGIONID_MASK          REG_GENMASK(7, 0)
-#define OROM_OFFSET                            _MMIO(0x1020c0)
-#define   OROM_OFFSET_MASK                     REG_GENMASK(20, 16)
-
 #define MTL_MEDIA_GSI_BASE             0x380000
 
 #endif /* _I915_REG_H_ */
diff --git a/include/drm/intel/intel_gmd_common_regs.h 
b/include/drm/intel/intel_gmd_common_regs.h
index 01fffc983e47..59ea27228935 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -291,4 +291,12 @@
 #define   INSTPM_TLB_INVALIDATE        (1 << 9)
 #define   INSTPM_SYNC_FLUSH    (1 << 5)
 
+#define PRIMARY_SPI_TRIGGER                    _MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS                    _MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID                   _MMIO(0x102084)
+#define SPI_STATIC_REGIONS                     _MMIO(0x102090)
+#define   OPTIONROM_SPI_REGIONID_MASK          REG_GENMASK(7, 0)
+#define OROM_OFFSET                            _MMIO(0x1020c0)
+#define   OROM_OFFSET_MASK                     REG_GENMASK(20, 16)
+
 #endif
-- 
2.50.1

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