On Wed, 17 Dec 2025, Uma Shankar <[email protected]> wrote: > Extract South Chicken registers to common header. > This allows intel_pch_refclk.c not to include i915_reg.h
Why not intel_display_regs.h? > > Signed-off-by: Uma Shankar <[email protected]> > --- > .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 27 ------------------- > include/drm/intel/intel_gmd_common_regs.h | 27 +++++++++++++++++++ > 3 files changed, 28 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c > b/drivers/gpu/drm/i915/display/intel_pch_refclk.c > index 9a89bb6dcf65..55abb97c6562 100644 > --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c > +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c > @@ -4,8 +4,8 @@ > */ > > #include <drm/drm_print.h> > +#include <drm/intel/intel_gmd_common_regs.h> > > -#include "i915_reg.h" > #include "intel_de.h" > #include "intel_display_regs.h" > #include "intel_display_types.h" > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f60259c41c56..c1f33c11ac1b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1023,33 +1023,6 @@ > #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) > #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) > > -#define SOUTH_CHICKEN1 _MMIO(0xc2000) > -#define FDIA_PHASE_SYNC_SHIFT_OVR 19 > -#define FDIA_PHASE_SYNC_SHIFT_EN 18 > -#define INVERT_DDIE_HPD REG_BIT(28) > -#define INVERT_DDID_HPD_MTP REG_BIT(27) > -#define INVERT_TC4_HPD REG_BIT(26) > -#define INVERT_TC3_HPD REG_BIT(25) > -#define INVERT_TC2_HPD REG_BIT(24) > -#define INVERT_TC1_HPD REG_BIT(23) > -#define INVERT_DDID_HPD (1 << 18) > -#define INVERT_DDIC_HPD (1 << 17) > -#define INVERT_DDIB_HPD (1 << 16) > -#define INVERT_DDIA_HPD (1 << 15) > -#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) > * 2))) > -#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * > 2))) > -#define FDI_BC_BIFURCATION_SELECT (1 << 12) > -#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) > -#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) > -#define SBCLK_RUN_REFCLK_DIS (1 << 7) > -#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) > -#define SPT_PWM_GRANULARITY (1 << 0) > -#define SOUTH_CHICKEN2 _MMIO(0xc2004) > -#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) > -#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) > -#define LPT_PWM_GRANULARITY (1 << 5) > -#define DPLS_EDP_PPS_FIX_DIS (1 << 0) > - > #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) > #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) > #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) > diff --git a/include/drm/intel/intel_gmd_common_regs.h > b/include/drm/intel/intel_gmd_common_regs.h > index 4d91bc2dbb27..b4cfd186d5c0 100644 > --- a/include/drm/intel/intel_gmd_common_regs.h > +++ b/include/drm/intel/intel_gmd_common_regs.h > @@ -4,6 +4,33 @@ > #ifndef _INTEL_GMD_COMMON_REG_H_ > #define _INTEL_GMD_COMMON_REG_H_ > > +#define SOUTH_CHICKEN1 _MMIO(0xc2000) > +#define FDIA_PHASE_SYNC_SHIFT_OVR 19 > +#define FDIA_PHASE_SYNC_SHIFT_EN 18 > +#define INVERT_DDIE_HPD REG_BIT(28) > +#define INVERT_DDID_HPD_MTP REG_BIT(27) > +#define INVERT_TC4_HPD REG_BIT(26) > +#define INVERT_TC3_HPD REG_BIT(25) > +#define INVERT_TC2_HPD REG_BIT(24) > +#define INVERT_TC1_HPD REG_BIT(23) > +#define INVERT_DDID_HPD (1 << 18) > +#define INVERT_DDIC_HPD (1 << 17) > +#define INVERT_DDIB_HPD (1 << 16) > +#define INVERT_DDIA_HPD (1 << 15) > +#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) > * 2))) > +#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * > 2))) > +#define FDI_BC_BIFURCATION_SELECT (1 << 12) > +#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) > +#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) > +#define SBCLK_RUN_REFCLK_DIS (1 << 7) > +#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) > +#define SPT_PWM_GRANULARITY (1 << 0) > +#define SOUTH_CHICKEN2 _MMIO(0xc2004) > +#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) > +#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) > +#define LPT_PWM_GRANULARITY (1 << 5) > +#define DPLS_EDP_PPS_FIX_DIS (1 << 0) > + > #define _TRANSA_CHICKEN2 0xf0064 > #define _TRANSB_CHICKEN2 0xf1064 > #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, > _TRANSB_CHICKEN2) -- Jani Nikula, Intel
