On Wed, 17 Dec 2025, Uma Shankar <[email protected]> wrote: > Move CHICKEN_PIPESL_1 to common header to free intel_display.c > from including i915_reg.h
Same as before, I think this is display stuff that belongs under display, intel_clock_gating.c parts that use it belong in display/ too, and gvt can include the header directly. BR, Jani. > > Signed-off-by: Uma Shankar <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 23 -------------------- > include/drm/intel/intel_gmd_common_regs.h | 23 ++++++++++++++++++++ > 3 files changed, 24 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 9c6d3ecdb589..ad2782d85074 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -45,13 +45,13 @@ > #include <drm/drm_probe_helper.h> > #include <drm/drm_rect.h> > #include <drm/drm_vblank.h> > +#include <drm/intel/intel_gmd_common_regs.h> > > #include "g4x_dp.h" > #include "g4x_hdmi.h" > #include "hsw_ips.h" > #include "i915_config.h" > #include "i915_drv.h" > -#include "i915_reg.h" > #include "i9xx_plane.h" > #include "i9xx_plane_regs.h" > #include "i9xx_wm.h" > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c9fb9af1a35c..e807be4a9962 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -878,29 +878,6 @@ > #define CHICKEN_PAR2_1 _MMIO(0x42090) > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) > > -#define _CHICKEN_PIPESL_1_A 0x420b0 > -#define _CHICKEN_PIPESL_1_B 0x420b4 > -#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, > _CHICKEN_PIPESL_1_B) > -#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) > -#define HSW_PRI_STRETCH_MAX_X8 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) > -#define HSW_PRI_STRETCH_MAX_X4 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) > -#define HSW_PRI_STRETCH_MAX_X2 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) > -#define HSW_PRI_STRETCH_MAX_X1 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) > -#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) > -#define HSW_SPR_STRETCH_MAX_X8 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) > -#define HSW_SPR_STRETCH_MAX_X4 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) > -#define HSW_SPR_STRETCH_MAX_X2 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) > -#define HSW_SPR_STRETCH_MAX_X1 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) > -#define HSW_FBCQ_DIS REG_BIT(22) > -#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ > -#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ > -#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) > -#define SKL_PLANE1_STRETCH_MAX_X8 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) > -#define SKL_PLANE1_STRETCH_MAX_X4 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) > -#define SKL_PLANE1_STRETCH_MAX_X2 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) > -#define SKL_PLANE1_STRETCH_MAX_X1 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) > -#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ > - > #define DISP_ARB_CTL _MMIO(0x45000) > #define DISP_FBC_MEMORY_WAKE REG_BIT(31) > #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) > diff --git a/include/drm/intel/intel_gmd_common_regs.h > b/include/drm/intel/intel_gmd_common_regs.h > index d4f91703e8a0..1908c203d54c 100644 > --- a/include/drm/intel/intel_gmd_common_regs.h > +++ b/include/drm/intel/intel_gmd_common_regs.h > @@ -80,6 +80,29 @@ > #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) > #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) > > +#define _CHICKEN_PIPESL_1_A 0x420b0 > +#define _CHICKEN_PIPESL_1_B 0x420b4 > +#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, > _CHICKEN_PIPESL_1_B) > +#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) > +#define HSW_PRI_STRETCH_MAX_X8 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) > +#define HSW_PRI_STRETCH_MAX_X4 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) > +#define HSW_PRI_STRETCH_MAX_X2 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) > +#define HSW_PRI_STRETCH_MAX_X1 > REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) > +#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) > +#define HSW_SPR_STRETCH_MAX_X8 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) > +#define HSW_SPR_STRETCH_MAX_X4 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) > +#define HSW_SPR_STRETCH_MAX_X2 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) > +#define HSW_SPR_STRETCH_MAX_X1 > REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) > +#define HSW_FBCQ_DIS REG_BIT(22) > +#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ > +#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ > +#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) > +#define SKL_PLANE1_STRETCH_MAX_X8 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) > +#define SKL_PLANE1_STRETCH_MAX_X4 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) > +#define SKL_PLANE1_STRETCH_MAX_X2 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) > +#define SKL_PLANE1_STRETCH_MAX_X1 > REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) > +#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ > + > #define _TRANSA_CHICKEN2 0xf0064 > #define _TRANSB_CHICKEN2 0xf1064 > #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, > _TRANSB_CHICKEN2) -- Jani Nikula, Intel
