> Subject: [PATCH v2 03/15] drm/i915/cx0: Drop Cx0 crtc_state from HDMI > TMDS pll divider calculation > > Drop crtc_state from hdmi tmds calculation and replace with the parameters > that are only required. Follow-up changes will call these functions without a
Nit: Capitalize acronyms so HDMI,TMDS, PLL Otherwise LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > crtc_state available. > > v2: Keep required crtc_state param for intel_c20_pll_tables_get() > and other functions calling this one. > > Signed-off-by: Mika Kahola <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 +++++++++-------- > 1 file changed, 9 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 1deb865618b7..664c48dc0ce3 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2414,9 +2414,8 @@ static bool is_arrowlake_s_by_host_bridge(void) > return pdev && > IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id); > } > > -static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state > *crtc_state) > +static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_display *display) > { > - struct intel_display *display = to_intel_display(crtc_state); > u16 tx_misc; > u16 tx_dcc_cal_dac_ctrl_range = 8; > u16 tx_term_ctrl = 2; > @@ -2438,7 +2437,8 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(const > struct intel_crtc_state *crtc_stat > C20_PHY_TX_DCC_BYPASS | > C20_PHY_TX_TERM_CTL(tx_term_ctrl)); > } > > -static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state > *crtc_state, > +static int intel_c20_compute_hdmi_tmds_pll(struct intel_display *display, > + int port_clock, > struct intel_c20pll_state *pll_state) > { > u64 datarate; > @@ -2452,10 +2452,10 @@ static int > intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_s > u8 mpllb_ana_freq_vco; > u8 mpll_div_multiplier; > > - if (crtc_state->port_clock < 25175 || crtc_state->port_clock > > 600000) > + if (port_clock < 25175 || port_clock > 600000) > return -EINVAL; > > - datarate = ((u64)crtc_state->port_clock * 1000) * 10; > + datarate = ((u64)port_clock * 1000) * 10; > mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, > (u64)datarate)); > vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, > (u64)datarate)); > vco_freq = (datarate << vco_freq_shift) >> 8; @@ -2477,9 +2477,9 > @@ static int intel_c20_compute_hdmi_tmds_pll(const struct > intel_crtc_state *crtc_s > else > mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0; > > - pll_state->clock = crtc_state->port_clock; > + pll_state->clock = port_clock; > pll_state->tx[0] = 0xbe88; > - pll_state->tx[1] = intel_c20_hdmi_tmds_tx_cgf_1(crtc_state); > + pll_state->tx[1] = intel_c20_hdmi_tmds_tx_cgf_1(display); > pll_state->tx[2] = 0x0000; > pll_state->cmn[0] = 0x0500; > pll_state->cmn[1] = 0x0005; > @@ -2724,7 +2724,8 @@ static int intel_c20pll_calc_state(const struct > intel_crtc_state *crtc_state, > /* try computed C20 HDMI tables before using consolidated tables */ > if (!is_dp) > /* TODO: Update SSC state for HDMI as well */ > - err = intel_c20_compute_hdmi_tmds_pll(crtc_state, > &hw_state->cx0pll.c20); > + err = intel_c20_compute_hdmi_tmds_pll(display, crtc_state- > >port_clock, > + &hw_state->cx0pll.c20); > > if (err) > err = intel_c20pll_calc_state_from_table(crtc_state, encoder, > -- > 2.34.1
