On 17.09.18 17:04, Nir Geller wrote:
Hi there,
I'm developing over Sitara IDK am5728 with TI supplied PROCESSOR-SDK-LINUX-AM57X
version v05.00 and PROCESSOR-SDK-RTOS-AM57X version v05.00.
I'm using the jailhouse hypervisor and I'm able to run Linux in a root cell on
core 0 and a TI RTOS as an inmate on core 1.
Now I'm trying to set up a pci device to allow communication between the two
cores.
I have a realtek etheret adapter mounted on the PCI-E slot, and it is being used
by Linux.
After going through the examples and reading posts in the forum I adapted the
root cell configuration (pci_am57xx-evm.c attached).
I didn't understand how to figure out the .pci_mmconfig_base address.
In case of a virtual PCI host controller, like you configured, this address is
just some free range in the physical address space of your board.
When enabling the root cell I get a CONFIG_OF_OVERLAY error message, and no PCI
device appears in lspci -v:
root@am57xx-evm:~# modprobe jailhouse
root@am57xx-evm:~# jailhouse enable jail/pci_am57xx-evm.cell
Initializing Jailhouse hypervisor v0.7 (220-g2ad429b) on CPU 0
Code location: 0xf0000040
Page pool usage after early setup: mem 30/4072, remap 32/131072
Initializing processors:
CPU 0... OK
CPU 1... OK
Adding virtual PCI device 00:01.0 to cell "AM57XX-EVM"
Page pool usage after late setup: mem 43/4072, remap 38/131072
Activating hypervisor
[ 857.467894] jailhouse: CONFIG_OF_OVERLAY disabled
[ 857.472645] jailhouse: failed to add virtual host controller
[ 857.478334] The Jailhouse is opening.
root@am57xx-evm:~#
root@am57xx-evm:~# lspci -v
00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01)
(prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 170
Memory at 20100000 (64-bit, non-prefetchable) [size=1M]
Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
I/O behind bridge: 00001000-00001fff [size=4K]
Memory behind bridge: None
Prefetchable memory behind bridge: 20200000-202fffff [size=1M]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Kernel driver in use: pcieport
01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411
PCI Express Gigabit Ethernet Controller (rev 06)
Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI
Express Gigabit Ethernet Controller
Flags: bus master, fast devsel, latency 0, IRQ 179
I/O ports at 1000 [size=256]
Memory at 20204000 (64-bit, prefetchable) [size=4K]
Memory at 20200000 (64-bit, prefetchable) [size=16K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Endpoint, MSI 01
Capabilities: [b0] MSI-X: Enable- Count=4 Masked-
Capabilities: [d0] Vital Product Data
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Virtual Channel
Capabilities: [160] Device Serial Number 01-00-00-00-68-4c-e0-00
Kernel driver in use: ec_r8169
root@am57xx-evm:~#
How should I fix the root cell config? what should I be looking for?
You need to rebuild your kernel, enabling CONFIG_OF_OVERLAY there.
Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
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