Hi Jan, I'm using jailhouse v0.8, so pci_domain is not available. However, after commenting out linux,pci-domain = <0>; from pcie1_rc: pcie@51000000 in dra7.dtsi I get good results from lspci -v
root@am57xx-evm:~# lspci -v 0000:00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01) (prog-if 00 [Normal decode]) ... 0000:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 06) ... 0001:00:00.0 Unassigned class [ff00]: Red Hat, Inc Inter-VM shared memory Subsystem: Red Hat, Inc Inter-VM shared memory Flags: fast devsel Memory at 30100000 (64-bit, non-prefetchable) [size=256] Memory at <unassigned> (64-bit, non-prefetchable) Capabilities: [50] MSI-X: Enable- Count=1 Masked- Should I worry about the following output? [ 80.456250] PCI: bus0: Fast back to back transfers disabled Now I would like to pass interrupts between cells. I'm following Giovani Gracioli's thread https://groups.google.com/forum/#!topic/jailhouse-dev/L2sjyl1xFDg According to which I'm now using uio_ivshmem kernel module. When I enable the root cell the function pci_alloc_irq_vectors() fails because dev->irq is set to 0. I don't know if it is related at all, the dts file skips some irqs from linux / { ocp { pruss1_eth { status = "disabled"; }; pruss2_eth { status = "disabled"; }; crossbar_mpu: crossbar@4a002a48 { ti,irqs-skip = <10 44 127 129 133 134 135 136 137 139 140>; }; }; }; Attached is the root cell configuration file Is .vpci_irq_base related? # cat /proc/interrupts CPU0 CPU1 17: 0 0 CBAR 32 Level gp_timer 18: 0 0 GICv2 29 Level arch_timer 19: 6062 9046 GICv2 30 Level arch_timer 22: 0 0 CBAR 4 Level l3-dbg-irq 23: 0 0 WUGEN 10 Level l3-app-irq 25: 1 0 CBAR 232 Level dra7xx-pcie-main 26: 0 0 CBAR 233 Level dra7-pcie-msi 27: 1 0 CBAR 121 Level talert 29: 18 0 CBAR 8 Level omap-dma-engine 32: 0 0 CBAR 361 Level 43300000.edma_ccint 34: 0 0 CBAR 359 Level 43300000.edma_ccerrint 37: 0 0 CBAR 24 Level 4ae10000.gpio 38: 0 0 CBAR 25 Level 48055000.gpio 39: 0 0 CBAR 26 Level 48057000.gpio 40: 0 0 CBAR 27 Level 48059000.gpio 41: 0 0 CBAR 29 Level 4805d000.gpio 42: 0 0 CBAR 30 Level 48051000.gpio 43: 0 0 CBAR 116 Level 48053000.gpio 44: 461 0 CBAR 69 Level 48020000.serial 53: 77402 0 CBAR 34 Level mc_gp_timer 67: 2 0 CBAR 108 Level omap_dmm_irq_handler 68: 676 0 CBAR 51 Level 48070000.i2c 69: 6776 0 CBAR 78 Level mmc0 70: 490 0 CBAR 81 Level mmc1 71: 0 0 CBAR 23 Level 40d01000.mmu 72: 0 0 CBAR 145 Level 40d02000.mmu 73: 0 0 CBAR 395 Level 58882000.mmu 74: 0 0 CBAR 396 Level 55082000.mmu 77: 0 0 CBAR 49 Level ahci[4a140000.sata] 78: 0 0 CBAR 217 Level rtc1 79: 3 0 CBAR 72 Level dwc3-omap 80: 2 0 CBAR 87 Level dwc3-omap 82: 560 0 CBAR 335 Level 48484000.ethernet 83: 182 0 CBAR 336 Level 48484000.ethernet 91: 0 0 CBAR 46 Level 4b101000.sham 92: 0 0 CBAR 47 Level 48090000.rng 93: 0 0 CBAR 354 Level vpe 94: 0 0 CBAR 146 Level 41501000.mmu 95: 0 0 CBAR 147 Level 41502000.mmu 96: 0 0 CBAR 352 Level vip2-s0 97: 0 0 CBAR 393 Level vip2-s1 98: 0 0 WUGEN 131 Level arm-pmu 99: 0 0 WUGEN 132 Level arm-pmu 100: 0 0 CBAR 20 Level OMAP DISPC 101: 0 0 CBAR 96 Level OMAP HDMI 166: 0 0 4805d000.gpio 16 Level palmas 167: 0 0 palmas 8 Level 48070000.i2c:tps659038@58 :tps659038_rtc 170: 0 0 PCI-MSI 0 Edge PCIe PME, aerdrv 171: 0 0 pinctrl 584 Edge 48020000.serial 172: 0 0 48051000.gpio 12 Edge tpd12s015 hpd 173: 0 0 4805d000.gpio 27 Edge 4809c000.mmc cd 174: 0 0 48057000.gpio 16 Edge palmas_usb_id 176: 0 0 48057000.gpio 26 Edge palmas_usb_vbus 177: 0 0 CBAR 71 Level xhci-hcd:usb1 IPI0: 0 1 CPU wakeup interrupts IPI1: 0 0 Timer broadcast interrupts IPI2: 21693 26808 Rescheduling interrupts IPI3: 356 619 Function call interrupts IPI4: 0 0 CPU stop interrupts IPI5: 0 0 IRQ work interrupts IPI6: 0 0 completion interrupts Err: Thanks a lot, Nir. On Tue, Sep 18, 2018 at 11:12 AM Jan Kiszka <[email protected]> wrote: > On 18.09.18 10:06, Jan Kiszka wrote: > > On 18.09.18 09:57, Nir Geller wrote: > >> Thanks for your reply. > >> > >> I recompiled the kernel. > >> > >> Now when I try to enable the root cell I get this: > >> > >> [ 95.597454] OF: PCI: host bridge /vpci@0 ranges: > >> [ 95.602141] OF: PCI: MEM 0x30100000..0x30101fff -> 0x30100000 > >> [ 95.608155] pci-host-generic 30000000.vpci: ECAM at [mem > >> 0x30000000-0x300fffff] for [bus 00] > >> [ 95.622972] pci-host-generic 30000000.vpci: Node /vpci@0 has > inconsistent > >> "linux,pci-domain" property in DT > > > > Either your jailhouse system config needs to set .pci_domain for the > virtual > > host controller to 1, or you are missing linux,pci-domain in the device > tree > > entry of the physical controller of that target. Both device tree > entries need > > to be consistent /wrt this property, i.e. both use it or both leave it > out, > > that's what Linux means here. > > > > Oh, and the recommended variant is using linux,pci-domain because it gives > a > stable domain number across jailhouse disable / enable cycles. We are > slowly > converting boards (by adding patches for device trees that lack the entry). > > Jan > > -- > Siemens AG, Corporate Technology, CT RDA IOT SES-DE > Corporate Competence Center Embedded Linux > -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
/* * Jailhouse, a Linux-based partitioning hypervisor * * Copyright (c) Texas Insturments. Inc, 2016 * * Authors: * Vitaly Andrianov <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. */ #include <jailhouse/types.h> #include <jailhouse/cell-config.h> #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0]) struct { struct jailhouse_system header; __u64 cpus[1]; struct jailhouse_memory mem_regions[19]; struct jailhouse_irqchip irqchips[2]; struct jailhouse_pci_device pci_devices[1]; } __attribute__((packed)) config = { .header = { .signature = JAILHOUSE_SYSTEM_SIGNATURE, .revision = JAILHOUSE_CONFIG_REVISION, .hypervisor_memory = { .phys_start = 0xef000000, .size = 0x1000000, }, .debug_console = { .address = 0x48020000, .size = 0x1000, /* .divider = 26, */ .flags = JAILHOUSE_CON1_TYPE_8250 | JAILHOUSE_CON1_ACCESS_MMIO | JAILHOUSE_CON1_REGDIST_4 | JAILHOUSE_CON2_TYPE_ROOTPAGE, }, .platform_info = { .pci_mmconfig_base = 0x30000000, .pci_mmconfig_end_bus = 0, .pci_is_virtual = 1, .arm = { .gic_version = 2, .gicd_base = 0x48211000, .gicc_base = 0x48212000, .gich_base = 0x48214000, .gicv_base = 0x48216000, .maintenance_irq = 25, }, }, .root_cell = { .name = "AM57XX-EVM", .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), .num_irqchips = ARRAY_SIZE(config.irqchips), .num_pci_devices = ARRAY_SIZE(config.pci_devices), .vpci_irq_base = 134, }, }, .cpus = { 0x3, }, .mem_regions = { /* PCI */ { .phys_start = 0x20000000, .virt_start = 0x20000000, .size = 0x10000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* OCMCRAM */ { .phys_start = 0x40300000, .virt_start = 0x40300000, .size = 0x80000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* 0x40380000 - 0x48020000 */ { .phys_start = 0x40380000, .virt_start = 0x40380000, .size = 0x7ca0000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* UART... */ { .phys_start = 0x48020000, .virt_start = 0x48020000, .size = 0xe0000,//0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* 0x48100000 - 0x48281000 */ { .phys_start = 0x48100000, .virt_start = 0x48100000, .size = 0x110000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* * Leave gap for GIC controller 0x48210000 - 0x41220000 */ /* 0x48220000 - 0x48281000 */ { .phys_start = 0x48220000, .virt_start = 0x48220000, .size = 0x610000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* OMAP WakeupGen */ { .phys_start = 0x48281000, .virt_start = 0x48281000, .size = 0x1000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* PRCM MPU */ { .phys_start = 0x48243000, .virt_start = 0x48243000, .size = 0x1000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* 0x48400000 - 0x48424000 */ { .phys_start = 0x48400000, .virt_start = 0x48400000, .size = 0x24000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* UART... */ { .phys_start = 0x48424000, .virt_start = 0x48424000, .size = 0x2000,//0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* 0x48426000 - 0x48826000 */ { .phys_start = 0x48426000, .virt_start = 0x48426000, .size = 0x400000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* 0x48826000 - 0x48828000 */ { .phys_start = 0x48826000, .virt_start = 0x48826000, .size = 0x2000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* 0x48828000 - 0x4B300000 */ { .phys_start = 0x48828000, .virt_start = 0x48828000, .size = 0x2ad8000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* 0x4B500000 - 0x58000000 */ { .phys_start = 0x4B500000, .virt_start = 0x4B500000, .size = 0xCB00000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* Display Subsystem & ...*/ { .phys_start = 0x58000000, .virt_start = 0x58000000, .size = 0x8000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* RAM */ { .phys_start = 0x80000000, .virt_start = 0x80000000, .size = 0x6EE00000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE, }, /* IVSHMEM shared memory region for 02:00.0 */ { .phys_start = 0xEEE00000, .virt_start = 0xEEE00000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, }, /* communication region */ { .phys_start = 0xEEF00000, .virt_start = 0xEEF00000, .size = 0x00100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO, }, /* Leave hole for hypervisor */ /* RAM */ { .phys_start = 0xF0000000, .virt_start = 0xF0000000, .size = 0x10000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE, }, }, .irqchips = { /* GIC */ { .address = 0x48211000, .pin_base = 32, .pin_bitmap = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }, }, /* GIC */ { .address = 0x48211000, .pin_base = 160, .pin_bitmap = { 0xffffffff, 0, 0, 0 }, }, }, .pci_devices = { { /* 02:00.0 */ .type = JAILHOUSE_PCI_TYPE_IVSHMEM, /*.iommu = 1,*/ .bdf = 0 << 3, .bar_mask = { 0xffffff00, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, .num_msix_vectors = 1, .shmem_region = 16, .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, }, }, };
