Thanks for your reply.
I recompiled the kernel.
Now when I try to enable the root cell I get this:
[ 95.597454] OF: PCI: host bridge /vpci@0 ranges:
[ 95.602141] OF: PCI: MEM 0x30100000..0x30101fff -> 0x30100000
[ 95.608155] pci-host-generic 30000000.vpci: ECAM at [mem
0x30000000-0x300fffff] for [bus 00]
[ 95.622972] pci-host-generic 30000000.vpci: Node /vpci@0 has
inconsistent "linux,pci-domain" property in DT
[ 95.632989] pci-host-generic 30000000.vpci: PCI host bridge to bus
ffffffff:00
[ 95.640309] pci_bus ffffffff:00: root bus resource [bus 00]
[ 95.645915] pci_bus ffffffff:00: root bus resource [mem
0x30100000-0x30101fff]
[ 95.653206] pci ffffffff:00:02.0: [1af4:1110] type 00 class 0xff0000
[ 95.653243] pci ffffffff:00:02.0: reg 0x10: [mem 0x00000000-0x000000ff
64bit]
[ 95.653632] PCI: bus0: Fast back to back transfers disabled
[ 95.659250] pci ffffffff:00:02.0: BAR 0: assigned [mem
0x30100000-0x301000ff 64bit]
[ 95.667132] virtio-pci ffffffff:00:02.0: enabling device (0000 -> 0002)
root@am57xx-evm:~# lspci -v
lspci: sysfs_scan: Invalid domain ffffffff
root@am57xx-evm:~#
root@am57xx-evm:~# cat /proc/iomem
20013000-2fffffff : MEM
20100000-201fffff : 0000:00:00.0
20200000-202fffff : PCI Bus 0000:01
20200000-20203fff : 0000:01:00.0
20200000-20203fff : ec_r8169
20204000-20204fff : 0000:01:00.0
20204000-20204fff : ec_r8169
30000000-300fffff : PCI ECAM
30100000-30101fff : //vpci@0
30100000-301000ff : ffffffff:00:02.0
...
....
Is the problem related to bar_mask config?
How can I fix this?
What value should be assigned to .vpci_irq_base?
Thanks,
Nir.
On Tue, Sep 18, 2018 at 8:11 AM Jan Kiszka <[email protected]> wrote:
> On 17.09.18 17:04, Nir Geller wrote:
> >
> > Hi there,
> >
> >
> > I'm developing over Sitara IDK am5728 with TI supplied
> PROCESSOR-SDK-LINUX-AM57X
> > version v05.00 and PROCESSOR-SDK-RTOS-AM57X version v05.00.
> >
> > I'm using the jailhouse hypervisor and I'm able to run Linux in a root
> cell on
> > core 0 and a TI RTOS as an inmate on core 1.
> >
> > Now I'm trying to set up a pci device to allow communication between the
> two cores.
> > I have a realtek etheret adapter mounted on the PCI-E slot, and it is
> being used
> > by Linux.
> >
> > After going through the examples and reading posts in the forum I
> adapted the
> > root cell configuration (pci_am57xx-evm.c attached).
> >
> > I didn't understand how to figure out the .pci_mmconfig_base address.
>
> In case of a virtual PCI host controller, like you configured, this
> address is
> just some free range in the physical address space of your board.
>
> >
> > When enabling the root cell I get a CONFIG_OF_OVERLAY error message, and
> no PCI
> > device appears in lspci -v:
> >
> > root@am57xx-evm:~# modprobe jailhouse
> > root@am57xx-evm:~# jailhouse enable jail/pci_am57xx-evm.cell
> >
> > Initializing Jailhouse hypervisor v0.7 (220-g2ad429b) on CPU 0
> > Code location: 0xf0000040
> > Page pool usage after early setup: mem 30/4072, remap 32/131072
> > Initializing processors:
> > CPU 0... OK
> > CPU 1... OK
> > Adding virtual PCI device 00:01.0 to cell "AM57XX-EVM"
> > Page pool usage after late setup: mem 43/4072, remap 38/131072
> > Activating hypervisor
> > [ 857.467894] jailhouse: CONFIG_OF_OVERLAY disabled
> > [ 857.472645] jailhouse: failed to add virtual host controller
> > [ 857.478334] The Jailhouse is opening.
> > root@am57xx-evm:~#
> > root@am57xx-evm:~# lspci -v
> > 00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC
> (rev 01)
> > (prog-if 00 [Normal decode])
> > Flags: bus master, fast devsel, latency 0, IRQ 170
> > Memory at 20100000 (64-bit, non-prefetchable) [size=1M]
> > Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
> > I/O behind bridge: 00001000-00001fff [size=4K]
> > Memory behind bridge: None
> > Prefetchable memory behind bridge: 20200000-202fffff [size=1M]
> > Capabilities: [40] Power Management version 3
> > Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
> > Capabilities: [70] Express Root Port (Slot-), MSI 00
> > Capabilities: [100] Advanced Error Reporting
> > Kernel driver in use: pcieport
> >
> > 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
> RTL8111/8168/8411
> > PCI Express Gigabit Ethernet Controller (rev 06)
> > Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411
> PCI
> > Express Gigabit Ethernet Controller
> > Flags: bus master, fast devsel, latency 0, IRQ 179
> > I/O ports at 1000 [size=256]
> > Memory at 20204000 (64-bit, prefetchable) [size=4K]
> > Memory at 20200000 (64-bit, prefetchable) [size=16K]
> > Capabilities: [40] Power Management version 3
> > Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
> > Capabilities: [70] Express Endpoint, MSI 01
> > Capabilities: [b0] MSI-X: Enable- Count=4 Masked-
> > Capabilities: [d0] Vital Product Data
> > Capabilities: [100] Advanced Error Reporting
> > Capabilities: [140] Virtual Channel
> > Capabilities: [160] Device Serial Number 01-00-00-00-68-4c-e0-00
> > Kernel driver in use: ec_r8169
> >
> > root@am57xx-evm:~#
> >
> > How should I fix the root cell config? what should I be looking for?
>
> You need to rebuild your kernel, enabling CONFIG_OF_OVERLAY there.
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
>
--
You received this message because you are subscribed to the Google Groups
"Jailhouse" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/d/optout.
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Texas Insturments. Inc, 2016
*
* Authors:
* Vitaly Andrianov <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[19];
struct jailhouse_irqchip irqchips[2];
struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.hypervisor_memory = {
.phys_start = 0xef000000,
.size = 0x1000000,
},
.debug_console = {
.address = 0x48020000,
.size = 0x1000,
/* .divider = 26, */
.flags = JAILHOUSE_CON1_TYPE_8250 |
JAILHOUSE_CON1_ACCESS_MMIO |
JAILHOUSE_CON1_REGDIST_4 |
JAILHOUSE_CON2_TYPE_ROOTPAGE,
},
.platform_info = {
.pci_mmconfig_base = 0x30000000,
.pci_mmconfig_end_bus = 0,
.pci_is_virtual = 1,
.arm = {
.gic_version = 2,
.gicd_base = 0x48211000,
.gicc_base = 0x48212000,
.gich_base = 0x48214000,
.gicv_base = 0x48216000,
.maintenance_irq = 25,
},
},
.root_cell = {
.name = "AM57XX-EVM",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.vpci_irq_base = 86,
},
},
.cpus = {
0x3,
},
.mem_regions = {
/* PCI */ {
.phys_start = 0x20000000,
.virt_start = 0x20000000,
.size = 0x10000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* OCMCRAM */ {
.phys_start = 0x40300000,
.virt_start = 0x40300000,
.size = 0x80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* 0x40380000 - 0x48020000 */ {
.phys_start = 0x40380000,
.virt_start = 0x40380000,
.size = 0x7ca0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* UART... */ {
.phys_start = 0x48020000,
.virt_start = 0x48020000,
.size = 0xe0000,//0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* 0x48100000 - 0x48281000 */ {
.phys_start = 0x48100000,
.virt_start = 0x48100000,
.size = 0x110000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/*
* Leave gap for GIC controller 0x48210000 - 0x41220000
*/
/* 0x48220000 - 0x48281000 */ {
.phys_start = 0x48220000,
.virt_start = 0x48220000,
.size = 0x610000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* OMAP WakeupGen */ {
.phys_start = 0x48281000,
.virt_start = 0x48281000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* PRCM MPU */ {
.phys_start = 0x48243000,
.virt_start = 0x48243000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* 0x48400000 - 0x48424000 */ {
.phys_start = 0x48400000,
.virt_start = 0x48400000,
.size = 0x24000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* UART... */ {
.phys_start = 0x48424000,
.virt_start = 0x48424000,
.size = 0x2000,//0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* 0x48426000 - 0x48826000 */ {
.phys_start = 0x48426000,
.virt_start = 0x48426000,
.size = 0x400000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* 0x48826000 - 0x48828000 */ {
.phys_start = 0x48826000,
.virt_start = 0x48826000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* 0x48828000 - 0x4B300000 */ {
.phys_start = 0x48828000,
.virt_start = 0x48828000,
.size = 0x2ad8000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* 0x4B500000 - 0x58000000 */ {
.phys_start = 0x4B500000,
.virt_start = 0x4B500000,
.size = 0xCB00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Display Subsystem & ...*/ {
.phys_start = 0x58000000,
.virt_start = 0x58000000,
.size = 0x8000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* RAM */ {
.phys_start = 0x80000000,
.virt_start = 0x80000000,
.size = 0x6EE00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
/* IVSHMEM shared memory region for 02:00.0 */ {
.phys_start = 0xEEE00000,
.virt_start = 0xEEE00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED,
},
/* communication region */ {
.phys_start = 0xEEF00000,
.virt_start = 0xEEF00000,
.size = 0x00100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* Leave hole for hypervisor */
/* RAM */ {
.phys_start = 0xF0000000,
.virt_start = 0xF0000000,
.size = 0x10000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
},
.irqchips = {
/* GIC */ {
.address = 0x48211000,
.pin_base = 32,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* GIC */ {
.address = 0x48211000,
.pin_base = 160,
.pin_bitmap = {
0xffffffff, 0, 0, 0
},
},
},
.pci_devices = {
{ /* 02:00.0 */
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
/*.iommu = 1,*/
.bdf = 2 << 3,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.num_msix_vectors = 1,
.shmem_region = 16,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
},
},
};
