When the inmate cell is in AArch32 execution state, using mmio_read64()
to obtain the value of GICR_TYPER will cause error because mmio_read64()
generates "ldrd" instruction when compiling 32-bit gic_demo.bin, and
"ldrd" belongs to A64 assembly language which is cannot be used in
AArch32. So use mmio_read32() to read 64-bit GICR_ TYPER in twice.

In ARMv8-A, AArch64 state supports four levels of affinity. but AArch32
state can only support three levels of affinity. So use MPIDR_CPUID_MASK
to set bit[31:24] of mpidr to be 0, and ensure the correct mpidr.

Signed-off-by: Alice Guo <alice....@nxp.com>
---
 inmates/lib/arm-common/gic-v3.c         | 4 +++-
 inmates/lib/arm/include/asm/sysregs.h   | 2 ++
 inmates/lib/arm64/include/asm/sysregs.h | 2 ++
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/inmates/lib/arm-common/gic-v3.c b/inmates/lib/arm-common/gic-v3.c
index 35ee9a6a..cd202a46 100644
--- a/inmates/lib/arm-common/gic-v3.c
+++ b/inmates/lib/arm-common/gic-v3.c
@@ -76,6 +76,7 @@ static int gic_v3_init(void)
        map_range(redist_addr, PAGE_SIZE, MAP_UNCACHED);
 
        arm_read_sysreg(MPIDR, mpidr);
+       mpidr &= MPIDR_CPUID_MASK;
        aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
@@ -87,7 +88,8 @@ static int gic_v3_init(void)
                if (GICR_PIDR2_ARCH(pidr) != 3)
                        break;
 
-               typer = mmio_read64(redist_addr + GICR_TYPER);
+               typer = mmio_read32(redist_addr + GICR_TYPER);
+               typer |= (u64)mmio_read32(redist_addr + GICR_TYPER + 4) << 32;
                if ((typer >> 32) == aff) {
                        gicr = redist_addr;
                        break;
diff --git a/inmates/lib/arm/include/asm/sysregs.h 
b/inmates/lib/arm/include/asm/sysregs.h
index 72cabdc5..c0b137c7 100644
--- a/inmates/lib/arm/include/asm/sysregs.h
+++ b/inmates/lib/arm/include/asm/sysregs.h
@@ -77,6 +77,8 @@
 
 #define MPIDR          SYSREG_32(0, c0, c0, 5)
 
+#define  MPIDR_CPUID_MASK      0x00ffffff
+
 #define MPIDR_LEVEL_BITS               8
 #define MPIDR_LEVEL_MASK               ((1 << MPIDR_LEVEL_BITS) - 1)
 #define MPIDR_LEVEL_SHIFT(level)       (MPIDR_LEVEL_BITS * (level))
diff --git a/inmates/lib/arm64/include/asm/sysregs.h 
b/inmates/lib/arm64/include/asm/sysregs.h
index 8065b89d..6d94a59f 100644
--- a/inmates/lib/arm64/include/asm/sysregs.h
+++ b/inmates/lib/arm64/include/asm/sysregs.h
@@ -75,6 +75,8 @@
 
 #define MPIDR  MPIDR_EL1
 
+#define MPIDR_CPUID_MASK       0xff00ffffffUL
+
 #define MPIDR_LEVEL_BITS_SHIFT 3
 #define MPIDR_LEVEL_BITS       (1 << MPIDR_LEVEL_BITS_SHIFT)
 #define MPIDR_LEVEL_MASK       ((1 << MPIDR_LEVEL_BITS) - 1)
-- 
2.17.1

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