> -----Original Message-----
> From: Jan Kiszka <jan.kis...@siemens.com>
> Sent: 2020年8月14日 21:48
> To: Alice Guo <alice....@nxp.com>; jailhouse-dev@googlegroups.com
> Cc: Peng Fan <peng....@nxp.com>
> Subject: [EXT] Re: [PATCH V2 4/4] configs: arm64: imx8dxl: add cell
> configuration
> files
>
> Caution: EXT Email
>
> On 15.08.20 21:09, Alice Guo wrote:
> > Add imx8dxl-gic-demo-aarch32.c to support AArch32 VM on the imx8dxl
> > platform. Distinguish whether it is AArch32 inmate cell by the macro
> > JAILHOUSE_CELL_AARCH32.
> >
> > Add "imx8dxl-gic-demo-aarch64.c" for AArch64 VM.
> >
> > "imx8dxl.c" is used for the root cell.
> >
> > Signed-off-by: Alice Guo <alice....@nxp.com>
> > ---
> > configs/arm64/imx8dxl-gic-demo-aarch32.c | 64 +++++++++
> > configs/arm64/imx8dxl-gic-demo-aarch64.c | 64 +++++++++
>
> Sorry, missed that so far:
>
> Please add a imx8dxl-inmate-demo.c, instead of aarch64, and make sure it is in
> line with other inmate-demo configs. That will ease using this target with all
> kinds of inmates, including tests (once we have more...).
>
> And for the aarch32 variant: If the only difference is the flag, maybe put
> that in
> a define and include the imx8dxl-inmate-demo.c, rather than copying it. Will
> make maintenance easier.
[alice]:
Accoring your comment, add the following code to
configs/arm64/imx8dxl-gic-demo.c.
But it cannot work correctly because this file will not be compiled when
building for arm32. Do them need to be changed?
#if defined(CONFIG_ARM)
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG |
JAILHOUSE_CELL_AARCH32, #elif defined(CONFIG_ARM64)
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG, #endif
>
> > configs/arm64/imx8dxl.c | 173
> +++++++++++++++++++++++
> > 3 files changed, 301 insertions(+)
> > create mode 100644 configs/arm64/imx8dxl-gic-demo-aarch32.c
> > create mode 100644 configs/arm64/imx8dxl-gic-demo-aarch64.c
> > create mode 100644 configs/arm64/imx8dxl.c
> >
> > diff --git a/configs/arm64/imx8dxl-gic-demo-aarch32.c
> > b/configs/arm64/imx8dxl-gic-demo-aarch32.c
> > new file mode 100644
> > index 00000000..80dbd366
> > --- /dev/null
> > +++ b/configs/arm64/imx8dxl-gic-demo-aarch32.c
> > @@ -0,0 +1,64 @@
> > +/*
> > + * iMX8DXL target - gic-demo
> > + *
> > + * Copyright 2020 NXP
> > + *
> > + * Authors:
> > + * Alice Guo <alice....@nxp.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2.
> > +See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include <jailhouse/types.h>
> > +#include <jailhouse/cell-config.h>
> > +
> > +struct {
> > + struct jailhouse_cell_desc cell;
> > + __u64 cpus[1];
> > + struct jailhouse_memory mem_regions[3]; }
> > +__attribute__((packed)) config = {
> > + .cell = {
> > + .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
> > + .revision = JAILHOUSE_CONFIG_REVISION,
> > + .name = "gic-demo-aarch32",
> > + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG |
> JAILHOUSE_CELL_AARCH32,
> > + .cpu_set_size = sizeof(config.cpus),
> > + .num_memory_regions = ARRAY_SIZE(config.mem_regions),
> > + .num_irqchips = 0,
> > + .num_pci_devices = 0,
> > + .console = {
> > + .address = 0x5a060000,
> > + .type = JAILHOUSE_CON_TYPE_IMX_LPUART,
> > + .flags = JAILHOUSE_CON_ACCESS_MMIO |
> > + JAILHOUSE_CON_REGDIST_4,
> > + },
> > + },
> > +
> > + .cpus = {
> > + 0x2,
> > + },
> > +
> > + .mem_regions = {
> > + /* UART1 */ {
> > + .phys_start = 0x5a060000,
> > + .virt_start = 0x5a060000,
> > + .size = 0x1000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_IO |
> JAILHOUSE_MEM_ROOTSHARED,
> > + },
> > + /* RAM: Top at 4GB Space */ {
> > + .phys_start = 0xa1700000,
> > + .virt_start = 0,
> > + .size = 0x00100000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_EXECUTE |
> JAILHOUSE_MEM_LOADABLE,
> > + },
> > + /* communication region */ {
> > + .virt_start = 0x80000000,
> > + .size = 0x00001000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_COMM_REGION,
> > + },
> > + }
> > +};
> > diff --git a/configs/arm64/imx8dxl-gic-demo-aarch64.c
> > b/configs/arm64/imx8dxl-gic-demo-aarch64.c
> > new file mode 100644
> > index 00000000..88d436fe
> > --- /dev/null
> > +++ b/configs/arm64/imx8dxl-gic-demo-aarch64.c
> > @@ -0,0 +1,64 @@
> > +/*
> > + * iMX8DXL target - gic-demo
> > + *
> > + * Copyright 2020 NXP
> > + *
> > + * Authors:
> > + * Alice Guo <alice....@nxp.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2.
> > +See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include <jailhouse/types.h>
> > +#include <jailhouse/cell-config.h>
> > +
> > +struct {
> > + struct jailhouse_cell_desc cell;
> > + __u64 cpus[1];
> > + struct jailhouse_memory mem_regions[3]; }
> > +__attribute__((packed)) config = {
> > + .cell = {
> > + .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
> > + .revision = JAILHOUSE_CONFIG_REVISION,
> > + .name = "gic-demo",
> > + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
> > + .cpu_set_size = sizeof(config.cpus),
> > + .num_memory_regions = ARRAY_SIZE(config.mem_regions),
> > + .num_irqchips = 0,
> > + .num_pci_devices = 0,
> > + .console = {
> > + .address = 0x5a060000,
> > + .type = JAILHOUSE_CON_TYPE_IMX_LPUART,
> > + .flags = JAILHOUSE_CON_ACCESS_MMIO |
> > + JAILHOUSE_CON_REGDIST_4,
> > + },
> > + },
> > +
> > + .cpus = {
> > + 0x2,
> > + },
> > +
> > + .mem_regions = {
> > + /* UART1 */ {
> > + .phys_start = 0x5a060000,
> > + .virt_start = 0x5a060000,
> > + .size = 0x1000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_IO |
> JAILHOUSE_MEM_ROOTSHARED,
> > + },
> > + /* RAM: Top at 4GB Space */ {
> > + .phys_start = 0xa1700000,
> > + .virt_start = 0,
> > + .size = 0x00100000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_EXECUTE |
> JAILHOUSE_MEM_LOADABLE,
> > + },
> > + /* communication region */ {
> > + .virt_start = 0x80000000,
> > + .size = 0x00001000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_COMM_REGION,
> > + },
> > + }
> > +};
> > diff --git a/configs/arm64/imx8dxl.c b/configs/arm64/imx8dxl.c new
> > file mode 100644 index 00000000..f94692bc
> > --- /dev/null
> > +++ b/configs/arm64/imx8dxl.c
> > @@ -0,0 +1,173 @@
> > +/*
> > + * i.MX8DXL Target
> > + *
> > + * Copyright 2020 NXP
> > + *
> > + * Authors:
> > + * Alice Guo <alice....@nxp.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2.
> > +See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include <jailhouse/types.h>
> > +#include <jailhouse/cell-config.h>
> > +
> > +struct {
> > + struct jailhouse_system header;
> > + __u64 cpus[1];
> > + struct jailhouse_memory mem_regions[15];
> > + struct jailhouse_irqchip irqchips[3];
> > + struct jailhouse_pci_device pci_devices[2]; }
> > +__attribute__((packed)) config = {
> > + .header = {
> > + .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> > + .revision = JAILHOUSE_CONFIG_REVISION,
> > + .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
> > + .hypervisor_memory = {
> > + .phys_start = 0xbfc00000,
> > + .size = 0x00400000,
> > + },
> > + .debug_console = {
> > + .address = 0x5a060000,
> > + .size = 0x1000,
> > + .flags = JAILHOUSE_CON_TYPE_IMX_LPUART |
> > + JAILHOUSE_CON_ACCESS_MMIO |
> > + JAILHOUSE_CON_REGDIST_4,
> > + .type = JAILHOUSE_CON_TYPE_IMX_LPUART,
> > + },
> > + .platform_info = {
> > + .pci_mmconfig_base = 0xbf700000,
> > + .pci_mmconfig_end_bus = 0x0,
> > + .pci_is_virtual = 1,
> > + .pci_domain = 0,
> > + .arm = {
> > + .gic_version = 3,
> > + .gicd_base = 0x51a00000,
> > + .gicr_base = 0x51b00000,
> > + .maintenance_irq = 25,
> > + },
> > + },
> > + .root_cell = {
> > + .name = "imx8dxl",
> > + .num_pci_devices =
> ARRAY_SIZE(config.pci_devices),
> > + .cpu_set_size = sizeof(config.cpus),
> > + .num_memory_regions =
> ARRAY_SIZE(config.mem_regions),
> > + .num_irqchips = ARRAY_SIZE(config.irqchips),
> > + .vpci_irq_base = 2, /* Not include 32 base */
>
> Is SPI 2 actually free on this board? Usually, those low IRQs are all in use.
> Just to
> double-check.
[alice]:
Yes, I have checked "i.MX 8DualXLite Applications Processor Reference Manual".
>
> > + },
> > + },
> > +
> > + .cpus = {
> > + 0x3,
> > + },
> > +
> > + .mem_regions = {
> > + /* IVHSMEM shared memory region for 00:00.0 (demo )*/ {
> > + .phys_start = 0xbf900000,
> > + .virt_start = 0xbf900000,
> > + .size = 0x1000,
> > + .flags = JAILHOUSE_MEM_READ,
> > + },
> > + {
> > + .phys_start = 0xbf901000,
> > + .virt_start = 0xbf901000,
> > + .size = 0x9000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE ,
> > + },
> > + {
> > + .phys_start = 0xbf90a000,
> > + .virt_start = 0xbf90a000,
> > + .size = 0x2000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE ,
> > + },
> > + {
> > + .phys_start = 0xbf90c000,
> > + .virt_start = 0xbf90c000,
> > + .size = 0x2000,
> > + .flags = JAILHOUSE_MEM_READ,
> > + },
> > + {
> > + .phys_start = 0xbf90e000,
> > + .virt_start = 0xbf90e000,
> > + .size = 0x2000,
> > + .flags = JAILHOUSE_MEM_READ,
> > + },
> > + /* IVSHMEM shared memory regions for 00:01.0
> (networking) */
> > + JAILHOUSE_SHMEM_NET_REGIONS(0xbfa00000, 0),
> > + /* MMIO (permissive): TODO: refine the map */ {
> > + .phys_start = 0x00000000,
> > + .virt_start = 0x00000000,
> > + .size = 0x80000000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_IO,
> > + },
> > + /* RAM */ {
> > + .phys_start = 0x80200000,
> > + .virt_start = 0x80200000,
> > + .size = 0x21d00000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_EXECUTE,
> > + },
> > + /* Inmate memory */{
> > + .phys_start = 0xa1700000,
> > + .virt_start = 0xa1700000,
> > + .size = 0x1e000000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE,
> > + },
> > + /* Loader */{
> > + .phys_start = 0xbfb00000,
> > + .virt_start = 0xbfb00000,
> > + .size = 0x100000,
> > + .flags = JAILHOUSE_MEM_READ |
> JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_EXECUTE,
> > + },
> > + },
> > +
> > + .irqchips = {
> > + /* GIC */ {
> > + .address = 0x51a00000,
> > + .pin_base = 32,
> > + .pin_bitmap = {
> > + 0xffffffff, 0xffffffff, 0xffffffff,
> > 0xffffffff,
> > + },
> > + },
> > + /* GIC */ {
> > + .address = 0x51a00000,
> > + .pin_base = 160,
> > + .pin_bitmap = {
> > + 0xffffffff, 0xffffffff, 0xffffffff,
> > 0xffffffff,
> > + },
> > + },
> > + /* GIC */ {
> > + .address = 0x51a00000,
> > + .pin_base = 288,
> > + .pin_bitmap = {
> > + 0xffffffff, 0xffffffff, 0xffffffff,
> > 0xffffffff,
> > + },
> > + },
> > + },
> > +
> > + .pci_devices = {
> > + { /* IVSHMEM 0000:00:00.0 (demo) */
> > + .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
> > + .domain = 0,
> > + .bdf = 0 << 3,
> > + .bar_mask =
> JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
> > + .shmem_regions_start = 0,
> > + .shmem_dev_id = 0,
> > + .shmem_peers = 3,
> > + .shmem_protocol =
> JAILHOUSE_SHMEM_PROTO_UNDEFINED,
> > + },
> > + { /* IVSHMEM 0000:00:01.0 (networking) */
> > + .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
> > + .domain = 0,
> > + .bdf = 1 << 3,
> > + .bar_mask =
> JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
> > + .shmem_regions_start = 5,
> > + .shmem_dev_id = 0,
> > + .shmem_peers = 2,
> > + .shmem_protocol =
> JAILHOUSE_SHMEM_PROTO_VETH,
> > + },
> > + },
> > +};
> >
>
> Will a linux inmate config follow?
[alice]:
Yes.
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence
> Center Embedded Linux
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