I'm having trouble generating a netlist that can be used in PCBnew. EEschema has decided that all C and R components should have pins A and B instead of 1 and 2. I'm using the default symbol libraries.
PCBnew can't find the right pins on the modules I've picked, and this means the ratsnest isn't complete - and the components aren't connected to anything. This keeps happening on new schematics... What am I doing wrong?
