Hi, I've had a look at your design.
I do not understand either the logic. You should have warnings always or never but not sometimes. I think bidirectional or input or output are not important to connect the tracks, they are only for information purposes (erc will warn 2 outputs connected to each other) or drawing purposes (in order to let us understand the eschema). I always connect global labels at the top level, so I have never been in your case. Edit the netlist and search the internal names of the signals SDA, SCL and IntIO. Signal names are internally "signal.number_of_sheet". Even though you may not have ERC errors, signals could be not connected the way you wish if they are named SDA.1 and SDA.2. Please, let me know any progress. Pedro. > Having trouble with the logic behind labels. > > Hi, > > I'm currently having a root sheet which contains some 8 sub sheets (one > of the sub sheets also contains two "sub sub sheets". > > I took the following screen shot of my KiCad EeSchema project: > > http://img221.imageshack.us/my.php?image=labelissuesrw0.png > <http://img221.imageshack.us/my.php?image=labelissuesrw0.png> > > One can see that several sub sheets contain the hierarchical sheet pins > "SDA" and "SCL". > > Hierarchical sheet pin "SDA" is a bidirectional signal, while > hierarchical sheet pin "SCL" is an input signal for all the sheets, > except for the FoxBoard sheet. That sheet is providing the "SDA" and > "SCL" lines. The hierarchical sheet pin "SDA" remains (of course) bidi, > while the hierarchical sheet pin "SCL" line is here an output, not an > input. > > All goes well, except that I have to add for some sheets, more in > particular sheet "MCP23017" and sheet "Eprom Memory Device", explicit > net names "SDA" and "SCL" --connected to their respective hierarchical > sheet pins-- to avoid having warnings/errors in the ERC check. > > I can't understand the logic behind this: > > For most sub sheets, the hierarchical sheet pins "SDA" and "SCL" are > apparently "automatically" connected to one another, but for the two > above mentioned sheets, I have to explicitly add a net label. > > Can anyone explain this behaviour? It's no problem to get n0 ERC > warnings/errors, but I will only be satisfied if I could understand why > there's a different behaviour between different sub sheets having the > same type/name of hierarchical sheet pin(s). > > The same is valid for the hierarchical sheet pin "IntIO": most of the > sheets don't need an explicit net name, except sub sheet "LCD Control". > Also here, I can't explain this behaviour. > > My assumption was that all the hierarchical sheet pins with the same > name on the same (sub)sheet(s), would automatically "see" each other > and hence also implicitly connect to each other as one and the same net. > But apparently, I'm missing some clue(s) here... > > What I can understand, is that the hierarchical sheet pins "OUT1" and > "OUT2" of the sub sheet "LCD Control" need net labels to connect to the > hierarchical sheet pins "IN1" and "IN2" of the sub sheet "Relais > Control", because here the names of the hierarchical sheet pins are > different... > > Would appreciate if someone could shine a light on this. > > Best rgds, > --Geert > > >
