--- In kicad-users@yahoogroups.com, "Geert Vancompernolle" <[EMAIL PROTECTED]> wrote: > > Please, let me know any progress. > > Will do!
Hi Pedro, As promised, I did some investigation/experiment with my electrical design and verified with the net list, as you suggested. I came to know that indeed, if there are no net labels connected to the hierarchical sheet pins of the sub sheets on the root sheet level, there are also no connections between those points in the generated net list. So, all those points are "dangling"... I'll explain with some examples from my design (see link <http://img221.imageshack.us/my.php?image=labelissuesrw0.png> to my root sheet level design in the initial message I've posted). 1. Hierarchical sheet pin "SDA" on sub sheet "Input/Output": See the following image of (a part of) the "inside" of sub sheet "Input/Output": http://img142.imageshack.us/my.php?image=inputoutputsdasd1.png <http://img142.imageshack.us/my.php?image=inputoutputsdasd1.png> In that sub sheet, there are 3 "SDA" lines, of which only one is shown in the above image. This is the content of the net list regarding the hierarchical sheet pin "SDA": ( /48F0CE90/45521C34 R3H R5 100 {Lib=R3H} ( 1 N-000207 ) ( 2 /Input/Output/SDA ) ) ( /48F0CE90/4552189A R3H R3 100 {Lib=R3H} ( 1 N-000205 ) ( 2 /Input/Output/SDA ) ) ( /48F0CE90/4550E62A R3H R1 100 {Lib=R3H} ( 1 N-000209 ) ( 2 /Input/Output/SDA ) ) That's all there is! As said before, there are 3 SDA net labels in the sub sheet "Input/Output" (but only one is shown in the above image), so the net list shows only those 3 internal connections (indicated in red). Those SDA lines are outside the sub sheet "Input/Output" nowhere connected, meaning they are dangling... 2. Hierarchical sheet pin "SDA" on sub sheet "FoxBoard": Since the sub sheet "FoxBoard" is providing the signal "SDA", one is expecting that this hierarchical sheet pin is connected to all the other hierarchical sheet pins having the same "SDA" name. But again, that's not the case. Here's the second "proof": See the following image of (a part of) the "inside" of sub sheet "FoxBoard": http://img122.imageshack.us/my.php?image=foxboardsdato4.png <http://img122.imageshack.us/my.php?image=foxboardsdato4.png> This is the content of the net list regarding the hierarchical sheet pin "SDA": ( /48F0CE88/4909B103 8dip300 U18 ADuM1250 {Lib=ADuM1250} ( 1 +3V3 ) ( 2 /FoxBoard/SDA_F ) ( 3 /FoxBoard/SCL_F ) ( 4 GND ) ( 5 GND ) ( 6 /FoxBoard/SCL ) ( 7 /FoxBoard/SDA ) ( 8 +5V ) ) ( /48F0CE88/4904B091 R3H R187 4k7 {Lib=R3H} ( 1 +5V ) ( 2 /FoxBoard/SDA ) ) Again, that's all there is! One can see that also here, the "internal" connections between the different net labels "SDA" are made in the sub sheet "FoxBoard", but externally they're going nowhere, while they should be connected to some 5-10 other hierarchical sub sheet pins with the same "SDA" name... 3. Hierarchical sheet pin "SDA" on sub sheet "Eeprom Memory Device": See the following image of (a part of) the "inside" of sub sheet "Eeprom Memory Device": http://img220.imageshack.us/my.php?image=eeprommemorydevicesdaze3.png <http://img220.imageshack.us/my.php?image=eeprommemorydevicesdaze3.png> This is a case where things do go right, since the sub sheet "Eeprom Memory Devices" has a net label connected to the hierarchical sheet pin "SDA" on the root sheet level. This is the content of the net list regarding the hierarchical sheet pin "SDA": ( /48F0CE8C/455616DD R3H R71 100 {Lib=R3H} ( 1 N-000124 ) ( 2 /SDA ) ) ( /49049CF8/49049EFE R3H R169 100 {Lib=R3H} ( 1 N-000233 ) ( 2 /SDA ) ) This is a very interesting one: The first block in the above net list output shows the connection of R71 (part of the sub sheet "Eeprom Memory Device") to the net label "SDA" (later on, we will see that this is the name of the root sheet level net name, not the internal sub sheet net name!). But then, where is the second block suddenly coming from? Well, if you look carefully to the overall root sheet, you'll see that there's another sub sheet having a hierarchical sheet pin "SDA" connected to the same net name "SDA": the sub sheet "MCP23017". When looking into that sub sheet (see image http://img91.imageshack.us/my.php?image=mcp23017sdadc4.png <http://img91.imageshack.us/my.php?image=mcp23017sdadc4.png> ), then we see that indeed also R169 is connected to the (root sheet level) net name "SDA"! So, those two resistors (R71 and R169) are connected to each other via the root sheet level net name "SDA"!!! To prove that it's the root sheet level net name and not the sub sheet (internal) net name who's taking care of "connecting" different hierarchical sheet pins with the same name on the level of the root sheet, I've modified the net name of both hierarchical sheet pins "SDA" of the sub sheets "Eeprom Memory Device" and "MCP23017" into "SDA11". This is the result of the net list generation in that case: ( /48F0CE8C/455616DD R3H R71 100 {Lib=R3H} ( 1 N-000124 ) ( 2 /SDA11 ) ) ( /49049CF8/49049EFE R3H R169 100 {Lib=R3H} ( 1 N-000233 ) ( 2 /SDA11 ) ) Hence, despite the fact that internally in both sub sheets the net name "SDA" is used, it's the net name connected to the hierarchical sheet pins of the sub sheets on root sheet level that makes the connection! So, that "proves" the following: In absence of a net label connected to a sub sheet hierarchical sheet pin on the root sheet level, there's no connection between that sub sheet hierarchical sheet pin and the rest of the sub sheet hierarchical sheet pins with the same name on the root sheet! My conclusion: On root sheet level, you must add net names to the hierarchical sheet pins of sub sheets that needs to be connected together, otherwise you end up with dangling connections between the different sub sheets. Pls. feel free to contradict this conclusion, should I've overlooked something. Another conclusion: In one of my replies, I made the following assumption: I thought that sub sheets with hierarchical sheet pins having the same name, were implicitly connected by EeSchema. But that's clearly not the case, that has been proven above... However, that doesn't mean it's not a pity: if my assumption would have been true, it could have avoided root sheet "pollution" with the (currently necessary) net labels. Hope things are/were a bit clear in my above "investigation". Best rgds, --Geert
