On Thu, Jul 31, 2008 at 12:23:30AM -0400, [EMAIL PROTECTED] wrote:
Or, coming from the opposite end, is it possible to convert these opencores.org specs into something I'll understand like C or Python?
GHDL is a software VHDL simulator based around gcc. It is _very_ slow, but it works reasonably well for small projects. You could write a tool that would convert VHDL or Verilog into a C or Python simulation, but it would be much harder to understand than the original HW description source. I don't think you quite understand just how drastically different these languages are. They are not programming languages, they are hardware description languages. Generally most hardware designs are broken into fairly small pieces that are clock synchronized, since that is a lot easier for humans to deal with. But, every single one of these pieces happens simultaneously, since they are all separate pieces of real hardware. The "statements" describe the connection of signals. Usually, software people have a fairly hard time even writing simple hardware designs, because we are so conditioned to think of code as executing sequentially. VHDL even muddles this a bit by allowing sequences of statements that involve assignment. But, it isn't really sequential assignment, it just allows a kind of temporary variable shorthand to make things more readable. David -- [email protected] http://www.kernel-panic.org/cgi-bin/mailman/listinfo/kplug-list
