Avi Kivity wrote:
> Aurelien Jarno wrote:
>
>> On Fri, Oct 05, 2007 at 03:25:05PM +0200, Laurent Vivier wrote:
>>
>>
>>> Digging in the FreeBSD sources I found the origin of the problem:
>>>
>>> I added some ACPI traces:
>>>
>>> rsirq-0234 [13] RsIrqResource : Invalid interrupt
>>> polarity/trigger in
>>> resource list, 10
>>>
>>> Which is in /sys/contrib/dev/acpica/rsirq.c :
>>>
>>>
>>> /*
>>> * Check for HE, LL interrupts
>>> */
>>> switch (Temp8 & 0x09)
>>> {
>>> case 0x01: /* HE */
>>> OutputStruct->Data.Irq.EdgeLevel = ACPI_EDGE_SENSITIVE;
>>> OutputStruct->Data.Irq.ActiveHighLow = ACPI_ACTIVE_HIGH;
>>> break;
>>>
>>> case 0x08: /* LL */
>>> OutputStruct->Data.Irq.EdgeLevel = ACPI_LEVEL_SENSITIVE;
>>> OutputStruct->Data.Irq.ActiveHighLow = ACPI_ACTIVE_LOW;
>>> break;
>>>
>>> default:
>>> /*
>>> * Only _LL and _HE polarity/trigger interrupts
>>> * are allowed (ACPI spec, section "IRQ Format")
>>> * so 0x00 and 0x09 are illegal.
>>> */
>>> ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
>>> "Invalid interrupt polarity/trigger in resource list,
>>> %X\n", Tem
>>> p8));
>>> return_ACPI_STATUS (AE_BAD_DATA);
>>> }
>>>
>>>
>>>
>> Good catch!
>>
>>
>>
>>> Conclusion, in kvm-userspace/bios/acpi-dsdt.dsl, if you have "ActiveHigh",
>>> you
>>> must have "Edge" instead of "Level":
>>>
>>> - IRQ (Level, ActiveHigh, Shared)
>>> + IRQ (Edge, ActiveHigh, Shared)
>>>
>>> But I found nothing in ACPI specification explaining the freeBSD behavior.
>>>
>>>
>>>
>> It's actually described page 200 of the specifications (page 216 in
>> ACPIspec30.pdf):
>>
>> Note: This descriptor is meant for describing interrupts that are
>> connected to PIC-compatible
>> interrupt controllers, which can only be programmed for
>> Active-High-Edge-Triggered or Active-
>> Low-Level-Triggered interrupts. Any other combination is illegal. The
>> Extended Interrupt
>> Descriptor can be used to describe other combinations.
>>
>>
>>
>>
>>> Avi, if you think this anlysis is correct I can provide the patch changing
>>> "Level" to "Edge"...
>>>
>>>
>>>
>> It looks like the solution is either to describe the IRQ with an
>> "Extended Interrupt Descriptor" or to change this value to one of the
>> two allowed values. In the later case we have to make sure it is
>> consistent with the way the PIC works.
>>
>>
>>
>
> Edge-triggered means we can't share interrupt lines. Since we have only
> two or three that limits the number of devices we can have.
>
> So I'd like to try moving to active low pci interrupts, and implementing
> polarity in the qemu ioapic. It's probably closer to real hardware anyway.
>
>
>
The docs are conflicting. The piix3 spec describes the pic irqs
(PIRQ[A-D]#) as active low, but the internal pic describes level
interrupts as active high. There's probably an inverter in there somewhere.
--
Any sufficiently difficult bug is indistinguishable from a feature.
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