On Tue, Oct 30, 2001 at 12:07:34PM +0530, Harishankkar wrote: > Bit 18 says SMROM clock pin 0 (SDCLK 0) divide by 2 control /status. > Why should I check it ? Am I missing any thing here? >
Ooops! sory. What I meant was bit 22 (K1DB2) in MDREFR which controls the SDCLK 1 > I am having a Winbond W986416DH-7. The Tac is given as 5.5ns at CS=3 and > it is 6 ns at CS=2. Since I am running at 103.2 Mhz then Tmem=19.379ns > Tmem-7.2(for 133 Mhz processor) = ~12ns and hence I must be able to run at > half the clock speed but I am not able to. Yes, you should be able to run at half the clock speed without delayed latching! > So here my SDRAM's Toh=3ns hence it should run at half the clock > speed without trouble but it is not running. I see, still you should be able to run at ~60MHz nondelayed! > Also I would like to know about the Errata mentioned in April 2001 > specification update. Sory, I can't help you on this, write now. Maybe latter I'll be able to find some time to check it out. Regards npat -- Beware of bugs in the above code; I have only proved it correct, not tried it. -- Donald E. Knuth _______________________________________________ http://lists.arm.linux.org.uk/mailman/listinfo/linux-arm Please visit the above address for information on this list.
