Re: egcs 1.1.1 assembler output for 2.2. kernel compilation.

[Russell King - ARM Linux Admin]

Philip Blundell writes:
> Where is this documented?  The ARM says of LDRBT simply:
> 
> Notes 
>       Register Rn: 
>       Specifies the base register used by <post_indexed_addressing_mode>.
>       
>       Operand restrictions:
>       If the same register is specified for Rd and Rn the results are
>       UNPREDICTABLE.
> 
> This is on page 3-46.

Well, indeed the ARM ARM does seem to imply this.  If this is the case, then
IMHO that's another error in the ARM ARM (the ARM ARM has on average one
error per page), since it means any code using this could break between ARM2
or ARM3 processors and ARM6+.  The ARM2 data book says:

'In the case of post-indexed addressing, the write back bit is redundant,
since the old base value can be retained by setting the offset to zero.'

Hence, when specifing an offset of zero, since no writeback is performed,
the result is predictable.  However, the question now is, does this apply
to the later processors?  Have ARM updated their ARM to include this?
Did they purposely remove this?  Or what?
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