>Well, indeed the ARM ARM does seem to imply this. If this is the case, then
>IMHO that's another error in the ARM ARM (the ARM ARM has on average one
>error per page), since it means any code using this could break between ARM2
>or ARM3 processors and ARM6+. The ARM2 data book says:
OK. It wouldn't be the first time that code sequences that were allowed or
even advised in ARM2 times have subsequently been declared to be verboten, of
course -- the NV condition is an obvious example. Judging by the fact that
nobody has reported a problem I assume that current silicon does actually
execute such an LDRBT as expected even if it isn't required to by the
architecture specification.
>'In the case of post-indexed addressing, the write back bit is redundant,
>since the old base value can be retained by setting the offset to zero.'
Does it explicitly say that no writeback takes place? In terms of processor
architecture it is very different to say that an offset of zero results in no
writeback, as opposed to that an offset of zero results in the original value
being written back unchanged. From the perspective of the system architect I
can well imagine that making this behaviour unpredictable would be an
attractive idea.
>to the later processors? Have ARM updated their ARM to include this?
>Did they purposely remove this? Or what?
Would you like to talk to ARM Ltd and find out? I would do so myself but I'm
out of the country for the next week. Once we have a definitive answer we can
fix the kernel or the assembler as appropriate.
p.
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