In article <[EMAIL PROTECTED]>
Russell King - ARM Linux Admin <[EMAIL PROTECTED]> wrote:
> The ARM2 data book says:
>
> 'In the case of post-indexed addressing, the write back bit is
> redundant, since the old base value can be retained by setting the
> offset to zero.'
>
> Hence, when specifing an offset of zero, since no writeback is
> performed, the result is predictable. However, the question now is,
> does this apply to the later processors? Have ARM updated their ARM
> to include this? Did they purposely remove this? Or what?
I don't read the above quote as
"if the offset is 0, no writeback is performed",
rather as
"since 0 is added, it's as if no writeback had taken place".
Of course, interpretation may vary between processors. ;-) BTW, the RISC
OS Appendix on ARM assembler also says:
"A post-indexed LDR|STR where Rm=Rn must not be used (this instruction
is very difficult for the abort handler to unwind when late aborts are
configured - which do not prevent base writeback)."
IMHO egcs really ought to produce 'ldrbt r6,[r6,#0]' instead of
'ldrbt r6,[r6],#0'.
Cheers,
Richard
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