Re:
> I'm surprised to learn that AMD has ported the bug to the SC5x0
> series, as it has actually been known for years now (albeit only
> to some insiders; I found out the hard way only about 4 weeks ago).
Well... You needn't find this problem yourself since it's listed in the
errata and it's been mentioned both on the Usenet and on this list (I
forwarded a patch a year ago or so).
The SC520 errata says (Fix planned for the B0 stepping) :
<<When a Transmit Holding Register Empty interrupt is generated by a UART
(THRE bit set in UARTxLSR and ETHREI bit set in UARTxINTENB) it will
deassert when the UARTxINTID register is read.
To be 16450/550 compatible the interrupt should be reissued if the ETHREI
bit is subsequently cleared and then set. However, this is not happening on
either UART. The interrupt is not reissued nor does the UARTxINTID register
read a value of 2 (THRE interrupt).
When the next byte is written to the UARTxTHR register a new interrupt is
generated when the Transmitter Holding Register becomes empty again.>>
Oh, BTW, this info - the errata - is stamped as confidential information. BS
IMNSHO.
//Bj�rnen.
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