> > Well... You needn't find this problem yourself since it's listed in the
> > errata and it's been mentioned both on the Usenet and on this list (I
> > forwarded a patch a year ago or so).
>
> I did try to look for an errata for the AMD SC410 (which is the one I
use),
> but I didn't find any on the AMD web-site (probably for the reason you
> state at the bottom), and I only joined this list two months ago...
I didn't intend to sound condescending, this discussion just felt a bit
superfluous considering we've been through this already ;) I mailed the
original author Ingvald 'Are you using AMD SC4x0? Use patch.blabla' just a
couple of minutes after the original request but probably forgot to CC the
list as well.
> > The SC520 errata says (Fix planned for the B0 stepping) :
> >
> > <<When a Transmit Holding Register Empty interrupt is generated by a
UART
> > (THRE bit set in UARTxLSR and ETHREI bit set in UARTxINTENB) it will
> > deassert when the UARTxINTID register is read.
>
> That, in itself, is not an error.
No :) Thats a description of how it works. I _much_ prefer simply reading
the IIR, jmp jmp_table[IIR_val] and looping back. The interrupts gets nicely
prioritised and served. I'm not sure why the serial code is written as it is
in the kernel.
//Bj�rnen.
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